ICS98ULPA877A 1.8V Low-Power Wide-Range Frequency Clock Driver Pin Configuration Recommended Application: 12 345 6 DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR2 DIMM logic solution A B Product Description/Features: C Low skew, low jitter PLL clock driver D 1 to 10 differential clock distribution (SSTL 18) E Feedback pins for input to output synchronization F Spread Spectrum tolerant inputs G Auto PD when input signal is at a certain logic state H J Switching Characteristics: K Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800) 52-Ball BGA Half-period jitter: 60ps (DDR2-400/533) Top View 50ps (DDR2-667/800) 12 34 5 6 OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 30ps (DDR2-667/800) B CLKC1 GND GND GND GND CLKC6 C CLKC2 GND NB NB GND CLKC7 CYCLE - CYCLE jitter 40ps D CLKT2 VDDQ VDDQ VDDQ OS CLKT7 E CLK INT VDDQ NB NB VDDQ FB INT F CLK INC VDDQ NB NB OE FB INC G AGND VDDQ VDDQ VDDQ VDDQ FB OUTC H AVDD GND NB NB GND FB OUTT J CLKT3 GND GND GND GND CLKT8 K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8 Block Diagram (1) LD or OE POWER OE DOWN AND LD, OS, or OE CLKT0 OS TEST MODE CLKC0 AVDD PLL BYPASS LOGIC CLKT1 LD CLKC7 CLKC1 VDDQ 1 30 CLKT2 CLKT7 CLKC2 2 29 CLKC2 VDDQ CLKT2 3 28 CLKT3 CLK INT 4 27 FB INT CLKC3 26 FB INC CLKT4 CLK INC 5 25 CLKC4 FBOUTC VDDQ 6 CLKT5 CLK INT 24 FBOUTT AGND 7 CLK INC CLKC5 AVDD 8 23 VDDQ CLKT6 10K - 100K PLL 22 VDDQ 9 OE CLKC6 FBIN INT 21 CLKT7 GND 10 OS FBIN INC CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 NOTE: 1. The Logic Detect (LD) powers down the device 40-Pin MLF FBOUTT when a logic LOW is applied to both CLK INT and CLK INC. FBOUTC 1177F12/10/09 11 CLKC1 CLKT3 40 12 39 CLKT1 CLKC3 13 CLKT0 CLKC4 38 14 CLKC0 CLKT4 37 15 36 VDDQ VDDQ 16 35 CLKT9 CLKC5 17 34 CLKT5 CLKC9 18 CLKT6 CLKC8 33 CLKT8 19 32 CLKC6 VDDQ 20 31 VDDQICS98ULPA877A Pin Descriptions Terminal Electrical Description Name Characteristics AdGND Analog Groun Ground AV Analog power 1.8 V nominal DD CrLK INT Clock input with a (10K-100K Ohm) pulldown resisto Differential input CLK INC Complentary clock input with a (10K-100K Ohm) pulldown resistor Differential input FtB INT Feedback clock inpu Differential input FtB INC Complementary feedback clock inpu Differential input FtB OUTT Feedback clock outpu Differential output FtB OUTC Complementary feedback clock outpu Differential output O)E Output Enable (Asynchronous LVCMOS input OVS Output Select (tied to GND or)tLVCMOS inpu DDQ GdND Groun Ground V Logic and output power 1.8V nominal DDQ CsLKT 0:9 Clock output Differential outputs CsLKC 0:9 Complementary clock output Differential outputs NlB No bal The PLL clock buffer, ICS98ULPA877A, is designed for a V of 1.8 V, a AV of 1.8 V and differential data input and DDQ DD output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK INT, CLK INC) to ten differential pair of clock outputs (CLKT 0:9 , CLKC 0:9 ) and one differential pair feedback clock outputs (FB OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK INT, CLK INC), the feedback clocks (FB INT, FB INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB OUTT/FB OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or V . When OS is high, OE will function as described above. When DDQ OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB OUTT/FB OUTC). When AV DD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK INT, CLK INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB INT, FB INC) and the input clock pair (CLK INT, CLK INC) within the specified stabilization time t . STAB The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK INT, CLK INC) and the feedback clocks (FB INT, FB INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT 0:9 , CLKC 0:9 ). ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. 1177F12/10/09 2