9DBV0641AKILF Renesas

6-Output 1.8V PCIe Zero-Delay/Fanout 9DBV 0641 Clock Buffer with Zo = 100ohms D ATA S HE E T Description Features/Benefits The 9DBV0641 is a member of Renesas 1.8V Direct connection to 100 transmission lines saves 24 Very-Low-Power (VLP) PCIe family. It has integrated output resistors compared to standard PCIe devices terminations providing Zo = 100 for direct connection to 55mW typical power consumption in PLL mode minimal 100 transmission lines. The device has 6 output enables for power consumption clock management and 3 selectable SMBus addresses. Outputs can optionally be supplied from any voltage between 1.05 and 1.8V maximum power savings Recommended Application OE pins support DIF power management HCSL compatible differential input can be driven by 1.8V PCIe Gen15 Zero Delay/Fanout Buffer (ZDB/FOB) common clock sources Spread Spectrum tolerant allows reduction of EMI Output Features Programmable Slew rate for each output allows tuning for Six 1200 MHz Low-Power (LP) HCSL DIF pairs with various line lengths Zo = 100 Programmable output amplitude allows tuning for various application environments Key Specifications Pin/software selectable PLL bandwidth and PLL Bypass minimize phase jitter for each application DIF cycle-to-cycle jitter < 50ps Outputs blocked until PLL is locked clean system start-up DIF output-to-output skew < 50ps Configuration can be accomplished with strapping pins PCIe Gen5 CC additive phase jitter < 40fs RMS SMBus interface not required for device control 12kHz20MHz additive phase jitter = 156fs RMS at 3.3V tolerant SMBus interface works with legacy controllers 156.25MHz (typical) Space saving 5 5mm 40-VFQFPN minimal board space 3 selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram vOE(5:0) 6 DIF5 CLK IN SS- DIF4 Compatible PLL DIF3 vSADR DIF2 vHIBW BYPM LOBW DIF1 CONTROL CKPWRGD PD LOGIC DIF0 SDATA 3.3 SCLK 3.3 9DBV0641 R31DS0077EU0400 AUGUST 2, 2021 1 2021 Renesas Electronics Corporation CLK IN 9DBV0641 DATASHEET Pin Configuration 40 39 38 37 36 35 34 33 32 31 vSADR tri130 NC vHIBW BYPM LOBW 229 vOE3 FB DNC328 DIF3 FB DNC 427 DIF3 9DBV0641 VDDR1.8526 VDDIO CLK IN625 VDDA1.8 Paddle is GND CLK IN 724 vOE2 GNDDIG823 DIF2 SCLK 3.3922 DIF2 SDATA 3.3 10 21 vOE1 11 12 13 14 15 16 17 18 19 20 40-pin VFQFPN prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor 5mm x 5mm 0.4mm pin pitch SMBus Address Selection Table + Read/Write bit SADR Address x 0 1101011 State of SADR on first application of x M 1101100 CKPWRGD PD 1 1101101 x Power Management Table SMBus DIFx CKPWRGD PD CLK IN OEx Pin PLL OEx bit True O/P Comp. O/P 0 X X X Low Low Off 1 1 Running 0 X Low Low On 1 1 Running 1 0 Running Running On 1 1 Running 1 1 Low Low On 1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table. 6-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 100OHMS 2 R31DS0077EU0400 AUGUST 2, 2021 VDDDIG1.8 CKPWRGD PD VDDIO VDDIO vOE0 vOE5 DIF0 DIF5 DIF0 DIF5 VDD1.8 vOE4 VDDIO DIF4 DIF1 DIF4 DIF1 VDDIO NC VDD1.8