9DMU0441AKILF Renesas

2:4 1.5V PCIe Gen1-2-3 Clock Mux 9D M U 044 1 w/Zo=100ohms D A T A S H E E T General Description Features/Benefits The 9DMU0441 is a member of IDT s SOC-Friendly 1.5V LP-HCSL outputs w/integrated terminations saves 16 Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has resistors compared to standard HCSL outputs integrated output terminations providing Zo=100ohms for 1.5V operation 26mW typical power consumption direct connection to 100ohm transmission lines. Each of the 4 Selectable asynchronous or glitch-free switching allows outputs has its own dedicated OE pin for optimal system the mux to be selected at power up even if both inputs are control and power management. The part provides not running, then transition to glitch-free switching mode asynchronous and glitch-free switching modes. Spread Spectrum Compatible supports EMI reduction OE pins support DIF power management Recommended Application HCSL differential inputs can be driven by common clock 2:4 PCIe Gen1-2-3 clock multiplexer sources 1MHz to 167MHz operating frequency Space saving 24-pin 4x4mm VFQFPN minimal board Output Features space 4 Low-Power (LP) HCSL DIF pairs w/Zo=100 Key Specifications DIF add iti ve cycle-to-cycle jitter <5ps DIF phase jitter is PCIe Gen1-2-3 compliant Additive phase jitter 125MHz: 535fs rms typical (12kHz to 20MHz) DIF output-to-output skew <50ps Block Diagram , OE(3:0) 4 DIF3 DIF INA A DIF2 DIF1 DIF INB B vSW MODE DIF0 SEL A B 9DMU0441 REVISION A 09/24/14 19DMU0441 DATASHEET Pin Configuration DIF INB Power Management Table Power Connections DIFx OEx Pin DIF IN True O/P Comp. O/P 0 Running Running Running 1 Running Low Low Pin Descriptions 2:4 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 2 REVISION A 09/24/14