2:1 1.8V PCIe Gen1-2-3 Clock Mux 9DMV0131 DATASHEET Description Features The 9DMV0131 is a member of IDT s SOC-Friendly 1.8V LP-HCSL output saves 2 resistors compared to standard Very-Low-Power (VLP) PCIe Gen1-2-3 family. The output has HCSL output an OE pin for optimal system control and power 1.8V operation 12mW typical power consumption management. The part provides asynchronous or glitch-free Selectable asynchronous or glitch-free switching allows switching modes. the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode Typical Applications Spread Spectrum Compatible supports EMI reduction OE pin supports DIF power management 2:1 1.8V PCIe Gen1-2-3 Clock Mux HCSL differential inputs can be driven by common clock sources Output Features 1MHz to 200MHz operating frequency 1 Low-Power (LP) HCSL DIF pair Space saving 16-pin 3x3mm VFQFPN minimal board space Key Specifications DIF additive cycle-to-cycle jitter <5ps DIF phase jitter is PCIe Gen1-2-3 compliant 125MHz additive phase jitter 420fs rms typical (12kHz to 20MHz) Block Diagram OE0 DIF INA A DIF0 DIF INB B vSW MODE SEL A B 9DMV0131 OCTOBER 22, 2018 1 2018 Integrated Device Technology, Inc.9DMV0131 DATASHEET Pin Configuration 16 15 14 13 GNDR 1 VDD1.8 12 VDDR1.8 2 GND 11 9DMV0131 VDDR1.8 3 DIF0 10 GNDR 4 9 DIF0 5678 16-pin VFQFPN, 3x3 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor Note: Paddle may be connected to ground for thermal purposes. It is not required electrically. Power Management Table Power Connections DIFx Pin Number OEx Pin DIF IN Description True O/P Comp. O/P VDD GND 0 Running Running Running 21 Input A receiver analog 1 Running Low Low 34 Input B receiver analog 12 11 DIF outputs Pin Descriptions Pin Pin Name Type Pin Description 1 GNDR GND Analog Ground pin for the differential input (receiver) 1.8V power for differential input clock (receiver). This VDD should be treated as an Analog 2 VDDR1.8 PWR power rail and filtered appropriately. 1.8V power for differential input clock (receiver). This VDD should be treated as an Analog 3 VDDR1.8 PWR power rail and filtered appropriately. 4 GNDR GND Analog Ground pin for the differential input (receiver) 5 DIF INB IN HCSL Differential True input 6 DIF INB IN HCSL Differential Complement Input Switch Mode. This pin selects either asynchronous or glitch-free switching of the mux. Use asynchronous mode if 0 or 1 of the input clocks is running. Use glitch-free mode if both input 7vSW MODE IN clocks are running. This pin has an internal pull down resistor of ~120kohms. 0 = asynchronous mode 1 = glitch-free mode Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor. 8 OE0 IN 1 =disable outputs, 0 = enable outputs 9 DIF0 OUT Differential true clock output 10 DIF0 OUT Differential Complementary clock output 11 GND GND Ground pin. 12 VDD1.8 PWR Power supply, nominal 1.8V 13 NC N/A No Connection. Input to select differential input clock A or differential input clock B. This input has an internal 14 SEL A B IN pull-up resistor. 0 = Input B selected, 1 = Input A selected. 15 DIF INA IN HCSL Differential True input 16 DIF INA IN HCSL Differential Complement Input 2:1 1.8V PCIE GEN1-2-3 CLOCK MUX 2 OCTOBER 22, 2018 DIF INB DIF INA DIF INB DIF INA vSW MODE SEL A B OE0 NC