DATASHEET 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 9EX21801A Description Features/Benefits Supports output clock frequencies up to 400 MHz The 9EX21801 provides 18 output clocks for PCIe Gen2 (100MHz) or QPI (133MHz) applications. The 9EX21801 has 4 4 Selectable SMBus addresses selectable SMBus addresses, and dedicated CKPWRGD/PD SMBus address is independent of PLL operating mode and VDDA pins for easy board design. A differential CPU clock Dedicated CKPWRGD/PD and VDDA pins ease board from a CK410B+ main clock generator, such as the 932S421, design drives the 9EX21801. In fanout mode, the 9EX21801 provides Available in industrial temperature range (-40C to +85C) outputs up to 400MHz. Key Specifications DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 150 ps PCIe Gen2 compliant phase noise QPI 133MHz compliant phase noise Functional Block Diagram OE(17:15) 12 OE(14:5) , OE 01234 CLKA IN PLL CLKA IN (SS Compatible) 18 DIF(17:0) CLKB IN CLKB IN HIBW BYPM LOBW 100M 133M CKPWRGD/PD SMB A0 Logic SMB A1 SEL A B SMBDAT SMBCLK IREF IDT 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E 07/20/11 1OE 01234 VDD CLKB IN CLKB IN GND CLKA IN CLKA IN VDDA GNDA IREF DIF 17 DIF 17 DIF 16 DIF 16 OE15 17 VDD DIF 15 DIF 15 9EX21801A Datasheet 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD 1 54 DIF 6 OE10 2 53 DIF 6 DIF 10 3 52 OE6 DIF 10 4 51 DIF 5 OE11 5 50 DIF 5 DIF 11 6 49 OE5 DIF 11 7 48 DIF 4 OE12 8 47 DIF 4 DIF 12 9 46 DIF 3 9EX21801AKLF DIF 12 10 45 DIF 3 GND 11 44 GND VDD 12 43 VDD DIF 13 13 42 DIF 2 DIF 13 14 41 DIF 2 OE13 15 40 DIF 1 DIF 14 16 39 DIF 1 DIF 14 17 38 DIF 0 OE14 18 37 DIF 0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin MLF Frequency/Functionality Table Byte 0, Power Groups bit 2 Byte 0, Byte 0, Input DIF x Pin Number (100 133M bit 1 bit 0 MHz MHz Description VDD GND Latch) FSB FSA Notes 1 01 100.00 100.00 1 29 28 Main PLL, Analog 0 01 133.33 133.33 1 1,12,21,35,43,55 11,32,44 DIF clocks 01 1 166.67 166.67 2 01 0 200.00 200.00 2 00 0 266.67 266.67 2 Power Down Functionality 10 0 333.33 333.33 2 INPUTS OUTPUTS PLL State 11 0 400.00 400.00 2 CKPWRGD/PD Input DIF x 11 1 Reserved 1 Running Running ON 0X Hi-Z OFF Notes:100M 133M 1. Latch selects between 100 and 133 MHz. This is equivalent to FSC in CK410B+/CK509B FS table. SMBus Address Selection (pins 66, 67) 2. Writing Byte 0 bits (2:0) can select other frequencies. These frequencies are not characterized in PLL Mode SMB A1 SMB A0 Address 00 D4 HIBW BYPM LOBW Selection (Pin 63) 01 D6 State Voltage Mode 10 D8 Low <0.8V Low BW 11 DA Mid 1.2<Vin<1.8V Bypass High Vin > 2.0V High BW IDT 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E 07/20/11 2 OE9 DIF 9 DIF 9 CKPWRGD/PD SEL A B SMB A0 SMB A1 SMBDAT SMBCLK HIBW BYPM LOBW 100M 133M DIF 8 DIF 8 OE8 DIF 7 DIF 7 OE7 VDD