3.3V PCIe Gen15 Clock 9FGL02x1/04x1/06x1/08x1 Generator Family Datasheet Description Features Integrated terminations for 100 and 85 systems save 4 The 9FGL02x1/04x1/06x1/08x1 devices comprise a family of 3.3V resistors per output PCIe Gen15 clock generators. There are 2, 4, 6 and 8 outputs versions available and each differential output has a dedicated 112206 mW typical power consumption (at 3.3V) OE pin supporting PCIe CLKREQ functionality. V rail allows 35% power savings at optional 1.05V DDIO (9FGL06 and 9FGL08 only) PCIe Clocking Architectures Devices contain default configuration SMBus not required Common Clocked (CC) SMBus-selectable features allows optimization to customer Independent Reference (IR) with and without spread spectrum requirements: (SRIS, SRNS) Input polarity and pull-up/pull-downs Typical Applications Output slew rate and amplitude Servers/High-Performance Computing Output impedance (33, 85 or 100) for each output nVME Storage Contact factory for customized default configurations Networking 25MHz input frequency Accelerators OE pins support PCIe CLKREQ function Industrial Control Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread SMBus-selectable CC/SRIS -0.25% spread Output Features Clean switching between the CC/SRIS spread settings 2, 4, 6, or 8 100MHz PCIe output pairs DIF outputs blocked until PLL is locked clean system start-up One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) 2 selectable SMBus addresses support Space saving packages: See AN-891 for easy AC-coupling to other logic families 4 4 mm 24-VFQFPN (9FGL02x1) Key Specifications 5 5 mm 32-VFQFPN (9FGL04x1) 90fs RMS typical jitter (PCIe Gen5 CC) 5 5 mm 40-VFQFPN (9FGL06x1) < 50ps cycle-to-cycle jitter on differential outputs 6 6 mm 48-VFQFPN (9FGL08x1) < 50ps output-to-output skew on differential outputs 0ppm synthesis error on differential outputs Block Diagram VDDREF VDDO/ VDDA VDDDIG VDDXTAL VDDIO n+1 vOE(n:0) REF3.3 XIN/CLKIN 25 DIFn DIFn X2 SSC Capable 2 to 8 PLL outputs vSADR vSS EN tri Control CKPWRGD PD DIF0 Logic SDATA 3.3 DIF0 SCLK 3.3 GNDXTAL GNDDIG GND EPAD GNDREF 2020 Renesas Electronics Corporation 1 November 17, 20209FGL02x1/04x1/06x1/08x1 Datasheet Contents Description 1 PCIe Clocking Architectures . 1 Typical Applications . 1 Output Features 1 Key Specifications 1 Features 1 Block Diagram . 1 Pin Assignments 3 9FGL02x1 Pin Assignment . 3 9FGL04x1 Pin Assignment . 4 9FGL06x1 Pin Assignment . 5 9FGL08x1 Pin Assignment . 6 Pin Descriptions 6 Absolute Maximum Ratings . 9 Thermal Characteristics 9 Electrical Characteristics 10 Power Management 17 Test Loads . 17 Alternate Terminations 18 Crystal Characteristics 19 General SMBus Serial Interface Information . 20 How to Write . 20 How to Read . 20 Package Outline Drawings . 29 Marking Diagrams . 29 9FGL02 . 29 9FGL04 . 29 9FGL06 . 30 9FGL08 . 30 Ordering Information . 31 Revision History . 32 2020 Renesas Electronics Corporation 2 November 17, 2020