4 O/P 1.5V PCIe Gen1-2-3 Clock Generator 9FGU0431 DATASHEET Description Features/Benefits The 9FGU0431 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 8 resistors compared to standard PCIe clock family. The device has 4 output enables for clock PCIe device management, 2 different spread spectrum levels in addition to 39mW typical power consumption reduced thermal spread off and 2 selectable SMBus addresses. concerns OE pins support DIF power management Recommended Application Programmable Slew rate for each output allows tuning for various line lengths 1.5V PCIe Gen1-2-3 Clock Generator Programmable output amplitude allows tuning for various application environments Output Features DIF outputs blocked until PLL is locked clean system 4 - 100MHz Low-Power (LP) HCSL DIF pair start-up 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) Selectable 0%, -0.25% or -0.5% spread on DIF outputs support reduces EMI External 25MHz crystal supports tight ppm with 0 ppm synthesis error Key Specifications Configuration can be accomplished with strapping pins DIF cycle-to-cycle jitter <50ps SMBus interface not required for device control DIF output-to-output skew <50ps Selectable SMBus addresses multiple devices can easily DIF phase jitter is PCIe Gen1-2-3 compliant share an SMBus segment REF phase jitter is < 3.0ps RMS 3.3V tolerant SMBus interface works with legacy controllers Space saving 32-pin 5x5 mm VFQFPN minimal board space Block Diagram XIN/CLKIN 25 REF1.5 OSC X2 vOE(3:0) DIF3 SS Capable PLL DIF2 vSADR DIF1 vSS EN tri CKPWRGD PD CONTROL SDATA 3.3 LOGIC DIF0 SCLK 3.3 9FGU0431 OCTOBER 18, 2016 1 2016 Integrated Device Technology, Inc.9FGU0431 DATASHEET Pin Configuration 32 31 30 29 28 27 26 25 GNDXTAL 1 vOE2 24 XIN/CLKIN 25 2 23 DIF2 X2 3 DIF2 22 VDDXTAL1.5 4 VDDA1.5 21 9FGU0431 VDDREF1.5 5 GNDA 20 vSADR/REF1.5 6 19 DIF1 GNDREF 7 DIF1 18 GNDDIG 817vOE1 9 10111213 141516 32-pin VFQFPN, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table + Read/Write Bit SADR Address State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 41 XTAL Analog 57 REF Output 98, 30 Digital Power 16, 25 15, 26 DIF outputs 21 20 PLL Analog 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR 2 OCTOBER 18, 2016 VDDDIG1.5 vSS EN tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.5 VDDO1.5