8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator 9FGU0831 DATASHEET General Description Features/Benefits The 9FGU0831 is a member of IDT s 1.5V Ultra-Low-Power LP-HCSL outputs save 16 resistors compared to standard PCIe clock family. The device has 8 output enables for clock PCIe devices management, 2 different spread spectrum levels in addition to 50mW typical power consumption reduced thermal spread off and 2 selectable SMBus addresses. concerns Outputs can optionally be supplied from any voltage between 1.05 and 1.5V maximum power savings Recommended Application OE pins support DIF power management 1.5V PCIe Gen1-2-3 Clock Generator Programmable Slew rate for each output allows tuning for various line length Output Features Programmable output amplitude allows tuning for various 8 - 100MHz Low-Power (LP) HCSL DIF pairs application environments 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL) DIF outputs blocked until PLL is locked clean system support start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs reduces EM Key Specification External 25MHz crystal supports tight ppm with 0 ppm DIF cycle-to-cycle jitter <50ps synthesis error DIF output-to-output skew < 60ps Configuration can be accomplished with strapping pins DIF phase jitter is PCIe Gen1-2-3 compliant SMBus interface not required for device control REF phase jitter is < 3.0ps RMS Selectable SMBus addresses multiple devices can easily share an SMBus segment 3.3V tolerant SMBus interface works with legacy controllers Space saving 48-pin 6x6 mm VFQFPN minimal board space Functional Block Diagram vOE(7:0) REF1.5 XIN/CLKIN 25 OSC DIF7 X2 DIF6 DIF5 SS Capable PLL DIF4 vSADR DIF3 vSS EN tri DIF2 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9FGU0831 OCTOBER 18, 2016 1 2016 Integrated Device Technology, Inc.9FGU0831 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSS EN tri 1 36 DIF5 GNDXTAL 2 35 DIF5 XIN/CLKIN 25 3 34 vOE4 X2 4 33 DIF4 532DIF4 VDDXTAL1.5 VDDREF1.5631VDDIO 9FGU0831 vSADR/REF1.5 7 30 VDDA1.5 GNDREF 8 29 GNDA GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.5 12 25 vOE2 13 14 15 16 17 18 19 20 21 22 23 24 48-pin VFQFPN, 6x6 mm, 0.4mm pitch vv prefix indicates internal 60KOhm pull down resistor v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor Power Management Table SMBus DIFx CKPWRGD PD REF OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRGD PD is low, REF is Low. SMBus Address Selection Table SADR Address + Read/Write Bit x State of SADR on first application 0 1101000 of CKPWRGD PD 1 1101010 x Power Connections Pin Number Description VDD VDDIO GND 5 2 XTAL OSC 68 REF Power Digital (dirty) 12 9 Power 13,21,31,39, 20,38 22,29,40 DIF outputs 47 30 29 PLL Analog 8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR 2 OCTOBER 18, 2016 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.5 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.5 DIF2 vOE5