DATASHEET 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9FGV0241 Description Features/Benefits The 9FGV0241 is a 2-output very low power frequency Integrated terminations provide 100 differential Zo generator for PCIe Gen 1, 2, 3 and 4 applications with reduced component count and board space integrated output terminations providing Zo = 100 . The 1.8V operation reduced power consumption device has 2 output enables for clock management and OE pins support DIF power management supports 2 different spread spectrum levels in addition to LP-HCSL differential clock outputs reduced power and spread off. board space Programmable Slew rate for each output allows tuning Recommended Application for various line lengths PCIe Gen1-4 clock generation for Riser Cards, Storage, Programmable output amplitude allows tuning for Networking, JBOD, Communications, Access Points various application environments Output Features DIF outputs blocked until PLL is locked clean system start-up 2 0.7V low-power HCSL-compatible (LP-HCSL) DIF Selectable 0%, -0.25% or -0.5% spread on DIF outputs pairs with Zo = 100 reduces EMI 1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) External 25MHz crystal supports tight ppm with 0 ppm support synthesis error Key Specifications Configuration can be accomplished with strapping pins SMBus interface not required for device control DIF cycle-to-cycle jitter <50ps 3.3V tolerant SMBus interface works with legacy DIF output-to-output skew <50ps controllers DIF phase jitter is PCIe Gen1-2-3-4 compliant Space saving 4 x 4 mm 24-VFQFPN minimal board REF phase jitter is < 1.5ps RMS space Block Diagram vOE(1:0) 2 REF XIN/CLKIN 25 IDT 603-25-150JA4C or 603-25-150JA4I 25MHz X2 DIF1 SSC Capable PLL DIF0 vSADR vSS EN tri CKPWRGD PD Control Logic SDATA 3.3 SCLK 3.3 IDT 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1 9FGV0241 JUNE 6, 20199FGV0241 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Pin Configuration 24 23 22 21 20 19 X1 25 1 DIF1 18 X2 2 DIF1 17 9FGV0241 VDDXTAL1.8 3 VDDA1.8 16 connect vSADR/REF1.8 4 GNDA 15 epad to GND GNDREF 5 DIF0 14 GNDDIG 613DIF0 7 8 9 10 11 12 24-pin VFQFPN, 4x4 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write Bit State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit True O/P Comp. O/P 1 0 X Low Low Hi-Z 1 1 Running Running Running 1 0 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 35,24 XTAL, REF 76 Digital Power 11,20 10,21 DIF outputs 16 15 PLL Analog IDT 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2 9FGV0241 JUNE 6, 2019 VDDDIG1.8 GNDXTAL SCLK 3.3 vSS EN tri SDATA 3.3 CKPWRGD PD GND GND VDD1.8 VDD1.8 vOE0 vOE1