REF1.8 DATASHEET 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9FGV0431 Description Features/Benefits The 9FGV0431 is a 4-output very low-power clock 1.8V operation reduced power consumption generator for PCIe Gen 1, 2, 3 and 4 applications. The OE pins support DIF power management device has 4 output enables for clock management and LP-HCSL differential clock outputs reduced power and supports 2 different spread spectrum levels in addition to board space spread off. Programmable Slew rate for each output allows tuning for various line lengths Recommended Application Programmable output amplitude allows tuning for PCIe Gen1-4 clock generation for Riser Cards, Storage, various application environments Networking, JBOD, Communications, Access Points DIF outputs blocked until PLL is locked clean system Output Features start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs 4 0.7V low-power HCSL-compatible (LP-HCSL) DIF reduces EMI pairs External 25MHz crystal supports tight ppm with 0 ppm 1 1.8V LVCMOS REF output w/Wake-On-Lan synthesis error Key Specifications Configuration can be accomplished with strapping pins SMBus interface not required for device control DIF cycle-to-cycle jitter <50ps 3.3V tolerant SMBus interface works with legacy DIF output-to-output skew <50ps controllers DIF phase jitter is PCIe Gen1-2-3-4 compliant Space saving 5 x 5 mm 32-QFN minimal board space REF phase jitter is < 1.5ps RMS Selectable SMBus addresses multiple devices can easily share an SMBus segment Block Diagram X1 25 OSC X2 OE(3:0) 4 SS Capable PLL DIF(3:0) SADR SS EN tri CONTROL CKPWRGD PD LOGIC SDATA 3.3 SCLK 3.3 IDT 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1 9FGV0431 JUNE 6, 20199FGV0431 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR Pin Configuration 32 31 30 29 28 27 26 25 GNDXTAL 1 24 vOE2 XIN/CLKIN 25 2 23 DIF2 X2 3 22 DIF2 VDDXTAL1.8 4 21 VDDA1.8 9FGV0431 VDDREF1.8 5 20 GNDA vSADR/REF1.8 6 DIF1 19 GNDREF 7 18 DIF1 GNDDIG 817vOE1 9 1011121314 15 16 32-pin MLF, 5x5 mm, 0.5mm pitch prefix indicates internal 120KOhm pull up resistor v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table SADR Address + Read/Write Bit State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit OEx True O/P Comp. O/P 1 0X XLow Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD GND 41 XTAL Analog 57 REF Output 98, 30 Digital Power 16, 25 15, 26 DIF outputs 21 20 PLL Analog IDT 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2 9FGV0431 JUNE 6, 2019 VDDDIG1.8 vSS EN tri SCLK 3.3 CKPWRGD PD SDATA 3.3 GND vOE0 vOE3 DIF0 DIF3 DIF0 DIF3 GND GND VDDO1.8 VDDO1.8