8-Output Very Low-Power PCIe Gen 14 9FGV0831 Clock Generator DATASHEET Description Features/Benefits The 9FGV0831 is a member of IDT s SOC-friendly 1.8V very LP-HCSL outputs saves 16 resistors compared to low-power PCIe clock family. The device has 8 output standard PCIe devices enables for clock management, 2 different spread spectrum 62mW typical power consumption reduced thermal levels in addition to spread off, and 2 selectable SMBus concerns addresses. Outputs can optionally be supplied from any voltage between 1.05 and 1.8V maximum power savings Recommended Application OE pins support DIF power management Programmable slew rate for each output allows tuning for PCIe Gen14 clock generation for Riser Cards, Storage, various line lengths Networking, JBOD, Communications, Access Points Programmable output amplitude allows tuning for various application environments Output Features DIF outputs blocked until PLL is locked clean system 8 100MHz Low-Power (LP) HCSL DIF pair start-up 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) Selectable 0%, -0.25% or -0.5% spread on DIF outputs support reduces EMI External 25MHz crystal supports tight ppm with 0 ppm Key Specifications synthesis error Configuration can be accomplished with strapping pins DIF cycle-to-cycle jitter <50ps SMBus interface not required for device control DIF output-to-output skew <50ps 3.3V tolerant SMBus interface works with legacy controllers DIF phase jitter is PCIe Gen1-2-3-4 compliant Selectable SMBus addresses multiple devices can easily REF phase jitter is <1.5ps RMS share an SMBus segment Space saving 6 x 6 mm 48-VFQFPN minimal board space Block Diagram vOE(7:0) REF1.8 XIN/CLKIN 25 OSC DIF7 X2 DIF6 DIF5 SS Capable PLL DIF4 vSADR DIF3 vSS EN tri DIF2 CKPWRGD PD CONTROL LOGIC SDATA 3.3 DIF1 SCLK 3.3 DIF0 9FGV0831 JUNE 6, 2019 19FGV0831 DATASHEET Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSS EN tri 1 36 DIF5 GNDXTAL 2 35 DIF5 X1 25 3 34 vOE4 X2 4 33 DIF4 VDDXTAL1.8 5 32 DIF4 VDDREF1.8 6 31 VDDIO 9FGV0831 vSADR/REF1.8 7 30 VDDA1.8 GNDREF 8 29 GNDA GNDDIG 9 28 vOE3 SCLK 3.3 10 27 DIF3 SDATA 3.3 11 26 DIF3 VDDDIG1.812 25vOE2 13 14 15 16 17 18 19 20 21 22 23 24 6 x 6 mm 48-VFQFPN, 0.4mm pitch vv prefix indicates internal 60kOhm pull-down resistor v prefix indicates internal 120kOhm pull-down resistor prefix indicates internal 120kOhm pull-up resistor SMBus Address Selection Table SADR Address + Read/Write Bit State of SADR on first application 0 1101000 x of CKPWRGD PD 1 1101010 x Power Management Table SMBus DIFx CKPWRGD PD REF OE bit OEx True O/P Comp. O/P 1 0 X X Low Low Hi-Z 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD PD high. After this, when CKPWRG PD is low, REF is Low. Power Connections Pin Number Description VDD VDDIO GND 5 2 XTAL OSC 68REF Power Digital (dirty) 12 9 Power 13,21,31,39, 20,38 22,29,40 DIF outputs 47 30 29 PLL Analog 8-OUTPUT VERY LOW-POWER PCIE GEN 14 CLOCK GENERATOR 2 JUNE 6, 2019 VDDIO CKPWRGD PD vOE0 VDDIO DIF0 vOE7 DIF0 DIF7 vOE1 DIF7 DIF1 vOE6 DIF1 DIF6 VDD1.8 DIF6 VDDIO GND GND VDDIO DIF2 VDD1.8 DIF2 vOE5