9FGV0841AKILF Renesas

8-Output Very Low-Power PCIe Gen14 9FGV0841 Datasheet Clock Generator with Zo = 100ohms Description Features Direct connection to 100 transmission lines saves 32 The 9FGV0841 is a member of IDT s SOC-friendly 1.8V very resistors compared to standard PCIe devices low-power PCIe clock family. It has integrated output terminations providing Zo = 100 for direction connection to 100 transmission 62mW typical power consumption reduced thermal concerns lines. The device has 8 output enables for clock management, 2 Outputs can optionally be supplied from any voltage between different spread spectrum levels in addition to spread off, and 2 1.05V and 1.8V maximum power savings selectable SMBus addresses. OE pins support DIF power management LP-HCSL differential clock outputs reduced power and board Typical Applications space PCIe Gen14 clock generation for Riser Cards Programmable slew rate for each output allows tuning for Storage various line lengths Networking Programmable output amplitude allows tuning for various JBOD application environments Communications DIF outputs blocked until PLL is locked clean system start-up Access Points Selectable 0%, -0.25% or -0.5% spread on DIF outputs reduces EMI Output Features External 25MHz crystal supports tight ppm with 0 ppm synthesis error Eight 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with Zo = 100 Configuration can be accomplished with strapping pins SMBus interface not required for device control One 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support 3.3V tolerant SMBus interface works with legacy controllers Selectable SMBus addresses multiple devices can easily Key Specifications share an SMBus segment DIF cycle-to-cycle jitter < 50ps Space saving 6 6 mm 48-VFQFPN minimal board space DIF output-to-output skew < 50ps Available in Commercial (0 to +70C), Industrial (-40C to +85C) and Automotive Grade 2 (-40C to +105C) DIF phase jitter is PCIe Gen14 compliant temperature ranges REF phase jitter is < 1.5ps RMS Block Diagram 8 vOE(7:0) REF1.8 XIN/CLKIN 25 OSC DIF7 X2 DIF6 DIF5 SS Capable PLL DIF4 DIF3 vSADR DIF2 vSS EN tri Control Logic CKPWRGD PD DIF1 SDATA 3.3 DIF0 SCLK 3.3 2021 Renesas Electronics Corporation 1 August 20, 20219FGV0841 Datasheet Contents Description 1 Typical Applications . 1 Output Features 1 Key Specifications 1 Features 1 Block Diagram . 1 Pin Assignments 3 Pin Descriptions 3 Power Management . 5 Absolute Maximum Ratings . 6 Thermal Characteristics 6 Electrical Characteristics . 7 Clock Periods . 11 Crystal Characteristics 12 ITest Loads . 12 Alternate Terminations 13 General SMBus Serial Interface Information . 14 How to Write . 14 How to Read . 15 Package Outline Drawings . 18 Marking Diagrams . 18 Ordering Information . 19 Revision History . 19 2021 Renesas Electronics Corporation 2 August 20, 2021