9FGV1005A001LTGI Renesas

Low Phase-Noise, Low-Power Programmable PhiClock 9FGV1001C / 9FGV1005C Generators Datasheet Description Features 1.8V to 3.3V power supplies The 9FGV1001C / 9FGV1005C are members of the Renesas PhiClock programmable clock generator family. The devices are Individual 1.8V to 3.3V V for each output pair DDO optimized for low phase noise in non-spread spectrum Supports HCSL, LVDS and LVCMOS I/O standards applications such as Ethernet or PCI Express. Four user-defined HCSL utilizes Renesas LP-HCSL technology for improved configurations may be selected via two hardware select pins or performance, lower power and higher integration: two I2C bits, allowing easy software selection of the desired Programmable output impedance of 85 or 100 configuration. Supports LVPECL and CML logic with easy AC coupling. See Typical Applications application note AN-891 for alternate terminations On-board OTP supports up to 4 complete configurations High-performance Computing (HPC) 2 Configuration selected via strapping pins or I C Enterprise Storage including eSSDs Internal crystal load capacitors 10G / 25G / 100G Ethernet < 125mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1001C) Data Center Accelerators < 100mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1005C) Multiple XO replacement 2 4 programmable I C addresses: D0, D2, D4, D6 PCIe Clocking Architectures Easily configured with Renesas Timing Commander software or Web Configuration tool Common Clocked (CC) 4 4 mm 24-VFQFPN (9FGV1001) Independent Reference without spread spectrum (SRnS) 3 3 mm 16-LGA (9FGV1005) Output Features Integrated crystal option available 9FGV1001: 4 programmable output pairs plus 2 REF outputs Key Specifications 9FGV1005: 2 programmable output pairs plus 1 REF output 261fs RMS 12kHz20MHz typical phase jitter at 156.25M Hz 1 integer output frequency per configuration PCIe Gen5 jitter (CC) < 0.08ps RMS 1MHz325MHz differential outputs PCIe Gen5 jitter (SRNS) < 0.07ps RMS 1MHz200MHz single-ended outputs Block Diagram Consult factory if design requires REF1. VDDREFp 9FGV1001 REF1 XIN/CLKIN OSC vREF0 SEL I2C XO OUT3 Prog. 9FGV1001CQ and Output 9FGV1005CQ integrate the OUT3 crystal VDDO3 9FGV1001 OUT2 Prog. Output OUT2 INT INT VDDO2 DIV PLL OUT1 Prog. Output OUT1 vSEL0/SCL SMBus Factory VDDO1 vSEL1/SDA Engine Configuration OUT0 Prog. Output OEB OUT0 Control 9FGV1001 OEA VDDO0 Logic 2020 Renesas Electronics Corporation 1 October 29, 20209FGV1001C / 9FGV1005C Datasheet Contents Description 1 Typical Applications . 1 PCIe Clocking Architectures . 1 Output Features 1 Features 1 Key Specifications 1 Block Diagram . 1 9FGV1001 Pin Assignments and Descriptions 3 9FGV1005 Pin Assignments and Descriptions 5 Phase Noise Plots 7 Absolute Maximum Ratings . 8 Recommended Operating Conditions . 8 Electrical Characteristics . 9 I2C Bus Characteristics . 15 Test Loads . 16 Crystal Characteristics 18 Package Outline Drawings . 18 Thermal Characteristics . 19 Marking Diagrams . 20 Standard Configurations . 20 Ordering Information . 21 Revision History . 22 2020 Renesas Electronics Corporation 2 October 29, 2020