PCIe Gen15 Low-Power Programmable PhiClock 9FGV1002C / 9FGV1006C Generators Datasheet Description Features 1.8V to 3.3V power supplies The 9FGV1002C / 9FGV1006C are members of the Renesas PhiClock programmable clock generator family. These devices Individual 1.8V to 3.3V V for each output pair DDO are optimized for low phase noise spread-spectrum applications Supports HCSL, LVDS and LVCMOS I/O standards such as PCIe Express. The 9FGV1002C is a four-output device HCSL utilizes Renesas LP-HCSL technology for improved while the 9FGV1006C is a smaller two-output version. Four performance, lower power and higher integration: user-defined configurations may be selected via two hardware Programmable output impedance of 85 or 100 select pins or two I2C bits, allowing easy software selection of the desired configuration. Any one of the four OTP configurations may Supports LVPECL and CML logic with easy AC coupling see be specified as the default when operating in I2C mode. Four application note AN-891 for alternate terminations unique I2C addresses are available, allowing easy I2C access to On-board OTP supports up to 4 complete configurations multiple components. 2 Configuration selected via strapping pins or I C Internal crystal load capacitors Typical Applications < 125mW at 1.8V with LP-HCSL outputs at 100MHz High-performance Computing (HPC) (9FGV1002C) Enterprise Storage including eSSDs < 100mW at 1.8V with LP-HCSL outputs at 100MHz 10G / 25G / 100G Ethernet (9FGV1006C) Fiber Optic Modules 2 4 programmable I C addresses: D0, D2, D4, D6 NVLink Easily configured with Renesas Timing Commander software or Web Configuration tool PCIe Clocking Architectures 4 4 mm 24-VFQFPN with integrated crystal option Common Clocked (CC) (9FGV1002CQ) Independent Reference without spread spectrum (SRnS) 3 3 mm 16-LGA with integrated crystal option (9FGV1006CQ) Independent Reference with spread spectrum (SRIS) Programmable spread spectrum modulation frequency and Output Features amount 9FGV1002: 4 programmable output pairs plus 2 LVCMOS REF Key Specifications outputs 12kHz20MHz typical phase jitter at 156.25M (SSC off) 276ps 9FGV1006: 2 programmable output pairs plus 1 LVCMOS REF RMS output PCIe Gen4 jitter (CC) < 0.23ps RMS 1 integer, fractional or spread spectrum output frequency per configuration PCIe Gen5 jitter (CC) < 0.08ps RMS 1MHz325MHz LVDS or LP-HCSL outputs PCIe Gen5 jitter (SRIS) < 0.07ps RMS 2020 Renesas Electronics Corporation 1 November 30, 20209FGV1002C / 9FGV1006C Datasheet 9FGV1002C / 9FGV1006C Block Diagram Consult factory if design requires REF1. VDDREFp 9FGV1002 REF1 XIN/CLKIN OSC vREF0 SEL I2C XO OUT3 Prog. 9FGV1002CQ and Output 9FGV1006CQ i ntegrate the OUT3 crystal VDDO3 9FGV1002 OUT2 Prog. Output OUT2 FRAC PLL INT VDDO2 DIV (SSC) OUT1 Prog. Output OUT1 vSEL0/SCL SMBus Factory VDDO1 vSEL1/SDA Engine Configuration OUT0 Prog. Output OEB OUT0 Control 9FGV1002 OEA VDDO0 Logic Table 1. OE Mapping OE B:A OUT0 OUT1 OUT2 OUT3 REF0 REF1 00 Running Stopped Stopped Stopped Running Running 01 Running Running Stopped Stopped Running Running 10 Running Running Running Stopped Running Running 11 Running Running Running Running Running Running 2020 Renesas Electronics Corporation 2 November 30, 2020