DATASHEET 32-pin CK505 for Intel Systems ICS9LRS4103 Recommended Application: Features/Benefits: CK505 clock, 32-pin for 5 series Intel chipsets Supports spread spectrum modulation, default is 0.5% down spread Output Features: Uses external 14.318MHz crystal, external crystal load 1 - CPU differential low power push-pull pairs caps are required for frequency tuning 1 - SRC differential low power push-pull pairs Does not require external pass transistor for voltage 1 - Selectable 120MHz CK SSC Disp or 100 MHz SRC low regulator power push-pull pair Integrated 33 series resistors on differential outputs, 1 - SATA/SRC selectable differential low power push-pull pair Zo=50 1 - DOT differential low power push-pull pair 1 - REF, 14.318MHz Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps +/- 100ppm frequency accuracy on all outputs SRC are PCIe Gen2 compliant Table 1: CPU Frequency Select Table Pin Configuration FS C CPU SRC REF DOT L MHz MHz MHz MHz B0b7 0 (Default) 133.33 100.00 14.318 96.00 1 100.00 1. FS C is a low-threshold input.Please see V and V specifications in L IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 32 31 30 29 28 27 26 25 X1 CPUC0 1 24 X2 2 CPUT0 23 SEL 120M SMBCLK 3.3 GNDCPU 3 22 Pin 21 Pin 10/11 SMBDAT 3.3 4 SEL 120M 21 9LRS4103 VDD96 5 VDDSRC Pulled Low 120MHz 20 DOT96T SRC2C 6 19 Pulled High 100MHz DOT96C SRC2T 7 18 GND96 8 17 GNDSRC 9 10 11 12 13 14 15 16 SEL SATA NS Pin 31 Pin 14/15 0 100MHz nonSS 1 100MHz SS ** Internal Pull-Down Resistor IDT PC MAIN CLOCK 1520A03/16/10 1 GNDSSC GNDXTAL CK SSC DISP T SEL SATA NS CK SSC DISP C VDDXTAL VDDSSC GNDREF VDDSATA REF14.318M/FSLC** SRC1T/SATA NS T VDDREF14M SRC1C/SATA NS C CKPWRGD/PD 3.3 GNDSATA VDDCPUICS9LRS4103 PC MAIN CLOCK Pin Description Pin Pin Name Type Pin Description 1 X1 IN Crystal input, Nominally 14.318MHz. 2 X2 OUT Crystal output, Nominally 14.318MHzMHz. 3 SMBCLK 3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 4 SMBDAT 3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 5 VDD96 PWR Power pin for the DOT96MHz output 3.3V. True clock DOT96 output with integrated 33ohm series resistor. No 50ohm 6 DOT96T OUT resistor to GND needed. Complementary clock DOT96 output with integrated 33ohm series resistor. 7 DOT96C OUT No 50ohm resistor to GND needed. 8 GND96 PWR Ground pin for the DOT96MHz output. 9 GNDSSC PWR Ground pin for the CK SSC DISP output. True clock of CK SSC DISP (100MHz or 120MHz) output with integrated 10 CK SSC DISP T OUT 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of CK SSC DISP (100MHz or 120MHz) output with 11 CK SSC DISP C OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. 12 VDDSSC PWR Power pin for the CK SSC DISP output 3.3V 13 VDDSATA PWR Power pin for the SATA output 3.3V True clock of differential 0.8V push-pull SRC/SATA output with integrated 14 SRC1T/SATA NS T OUT 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC/SATA output with 15 SRC1C/SATA NS C OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. 16 GNDSATA PWR Ground pin for the SATA output. 17 GNDSRC PWR Ground pin for the SRC output. True clock of differential 0.8V push-pull SRC output with integrated 33ohm 18 SRC2T OUT series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with 19 SRC2C OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. 20 VDDSRC PWR Power pin for the SRC output 3.3V. 21 SEL 120M IN Selects pins 10/11 to be 120MHz or 100MHz.0 = 120MHz,1 = 100MHz. 22 GNDCPU PWR Ground pin for the CPU output. True clock of differential pair 0.8V push-pull CPU outputs with integrated 23 CPUT0 OUT 33ohm series resistor. No 50 ohm resistor to GND needed. Complementary clock of differential pair 0.8V push-pull CPU outputs with 24 CPUC0 OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. 25 VDDCPU PWR Power pin for the CPU output 3.3V Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN 26 CKPWRGD/PD 3.3 IN mode 27 VDDREF14M PWR Power pin for the REF output 3.3V Reference 14.318 MHz clock, which drives 3 loads on default / 3.3V tolerant 28 REF14.318M 3X/FSLC** I/O input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. 29 GNDREF PWR Ground pin for the REF output. 30 VDDXTAL PWR Power pin for XTAL 3.3V 31 SEL SATA NS IN Selects pin 14/15 to be SRC1 or SATA NS.0 = SATA NS,1 = SRC1 32 GNDXTAL PWR Ground pin for XTAL. IDT PC MAIN CLOCK 1520A03/16/10 2