HSP45102 Data Sheet April 25, 2007 FN2810.9 12-Bit Numerically Controlled Oscillator Features The Intersil HSP45102 is Numerically Controlled Oscillator 33MHz, 40MHz Versions (NCO12) with 32-bit frequency resolution and 12-bit output. 32-Bit Frequency Control With over 69dB of spurious free dynamic range and worst BFSK, QPSK Modulation case frequency resolution of 0.009Hz, the NCO12 provides significant accuracy for frequency synthesis solutions at a Serial Frequency Load competitive price. 12-Bit Sine Output The frequency to be generated is selected from two frequency Offset Binary Output Format control words. A single control pin selects which word is used to determine the output frequency. Switching from one 0.009Hz Tuning Resolution at 40MHz frequency to another occurs in one clock cycle, with a 6 clock Spurious Frequency Components <-69dBc pipeline delay from the time that the new control word is Fully Static CMOS loaded until t4-he new frequency appears on the output. Low Cost Two pins, P0-1, are provided for phase modulation. They are encoded and added to the top two bits of the phase Pb-Free Plus Anneal Available (RoHS Compliant) accumulator to offset the phase in 90 increments. Applications The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM. The output data Direct Digital Synthesis format is offset binary to simplify interfacing to D/A Modulation converters. Spurious frequency components in the output PSK Communications sinusoid are less than -69dBc. Related Products The NCO12 has applications as a Direct Digital Synthesizer - HI5731 12-Bit, 100MHz D/A Converter and modulator in low cost digital radios, satellite terminals, and function generators. Ordering Information TEMP. PKG. PART NUMBER PART MARKING RANGE (C) PACKAGE DWG. HSP45102SC-33 HSP45102SC-33 0 to +70 28 Ld SOIC (300 mil) M28.3 HSP45102SC-33Z (Note) HSP45102SC-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 HSP45102SC-40 HSP45102SC -40 0 to +70 28 Ld SOIC (300 mil) M28.3 HSP45102SC-40Z (Note) HSP45102SC-40Z 0 to +70 28 Ld SOIC (300 mil)(Pb-free) M28.3 HSP45102SI-3396 HSP45102SI -33 0 to +70 28 Ld SOIC (300 mil) (Tape and Reel) M28.3 HSP45102SI-33Z (Note) HSP45102SI-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.HSP45102 Block Diagram CLK PO-1 MSB/LSB 32 PHASE FREQUENCY 13 12 SFTEN PHASE SINE OFFSET CONTROL SD 32 ACCUMULATOR 13 ROM ADDER SECTION OUT0-11 SCLK LOAD TXFR ENPHAC SEL L/M Pinout HSP45102 (28 LEAD SOIC) TOP VIEW OUT6 1 28 OUT5 OUT7 2 27 OUT4 OUT8 3 26 OUT3 OUT9 4 25 OUT2 OUT10 5 24 OUT1 OUT11 6 23 OUT0 GND 7 22 V CC V 8 21 GND CC SEL L/M 9 20 P0 SFTEN 10 19 P1 MSB/LSB 11 18 LOAD ENPHAC 12 17 TXFR SD 13 16 CLK SCLK 14 15 GND FN2810.9 2 April 25, 2007