MC100ES6226AC Renesas

2.5v/3.3v Differential LVPECL 1:9 MC100ES6226 Clock Distribution Buffer and Clock Driver Product Discontinuance Notice Last Time Buy Expires on (12/7/2013) DATASHEET The MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock divider. Designed for most demanding clock distribution systems, the MC100ES6226 supports various applications requiring a large number of outputs to drive precisely aligned 2.5 V/3.3 V DIFFERENTIAL clock signals. Using SiGe technology and a fully differential architecture, the device offers LVPECL 1:9 CLOCK DISTRIBUTION superior digital signal characteristics and very low clock skew error. Target applications for BUFFER AND CLOCK DIVIDER this clock driver are high performance clock distribution systems for computing, networking and telecommunication systems. Features Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Selectable 1:1 or 1:2 frequency outputs FA SUFFIX LVPECL compatible differential clock inputs and outputs 32-LEAD LQFP PACKAGE LVCMOS compatible control inputs CASE 873A-03 Single 3.3V or 2.5V supply Max. 35ps maximum output skew (within output bank) Max. 50ps maximum device skew Supports DC operation and up to 3GHz (typ.) clock signals Synchronous output enable eliminating output runt pulse generation and metastability AC SUFFIX Standard 32-lead LQFP package 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE Industrial temperature range (-40C TO 85C) CASE 873A-03 32-lead Pb-free package available Functional Description ORDERING INFORMATION MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0GHz. Typical applications for the Device Package MC100ES6226 are primary clock distribution systems on backplanes of high-performance MC100ES6226FA LQFP-32 computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. MC100ES6226FAR2 LQFP-32 The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the MC100ES6226AC LQFP-32 (Pb-Free) requirement of a negative supply line. Each of the output banks of three differential clock MC100ES6226ACR2 LQFP-32 (Pb-Free) output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asynchronous control inputs. Any changes of the control inputs require a MR pulse for re-synchronization of the 2 outputs. MC100ES6226 DECEMBER 18, 2012 1 2012 Integrated Device Technology, Inc.MC100ES6226 Data Sheet 2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER BANK A V CC QA0 1 QA0 CLK QA1 QA1 CLK 2 QA2 QA2 BANK B QB0 MR QB0 QB1 QB1 QB2 QB2 FSEL0 BANK C FSEL1 QC0 QC0 QC1 QC1 QC2 QC2 Sync OE Figure 1. MC100ES6226 Logic Diagram 24 23 22 21 20 19 18 17 QA2 25 16 QC0 QA2 26 15 QC0 27 14 QC1 V CC 28 13 QC1 QA1 MC100ES6226 QA1 29 12 VCC 30 11 QC2 QA0 QA0 31 10 QC2 32 9 V V CC CC 123 4 56 78 Figure 2. 32-Lead Package Pinout (Top View) MC100ES6226 REVESION 5 DECEMBER 18, 2012 2 2012 Integrated Device Technology, Inc. FSEL0 QB0 FSEL1 QB0 GND V CC CLK QB1 CLK QB1 QB2 V CC QB2 OE V MR CC