DATASHEET CLOCK RECOVERY PLL MK1575-01 Description Pre-Configured Input/Output Frequency Combinations: The MK1575-01 is a clock recovery Phase-Locked Loop Telecom T/E Clock Modes (rising edge aligned): (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to Addr Input Output Clocks Clock accept a low-frequency reference clock to generate a high-frequency data or graphics pixel clock. External loop FS2:0 Clock (MHz) Type filter components allow tailoring of loop frequency response CLK1 CLK2 characteristics. For low jitter / phase noise requirements 000 8 kHz 3.088 1.544 T1 refer to the MK2069 products. 001 8 kHz 16.384 2.048 E1 010 8 kHz 34.368 17.184 E3 Features 011 8 kHz 44.736 22.368 T3 Long-term output jitter <2 nsec over 10 sec period Video Clock Modes (falling edge aligned): External PLL clock feedback path enable zero delay I/O clock skew configuration Addr Input Output Clocks Clock Selectable internal feedback divider provides popular FS2:0 Clock (MHz) Type telecom and video clock frequencies (see tables below) (kHz) CLK1 CLK2 Can optionally use external feedback divider to generate other output frequencies. 100 15.625 54 27 PAL 601 Single 3.3 V supply, low-power CMOS 101 15.734 54 27 NTSC 601 Power-down mode and output tri-state (pin OE) 110 15.625 35.468 17.734 PAL 4xf sc Packaged in 16-pin TSSOP 111 15.734 28.636 14.318 NTSC 4xf sc Pb (lead) free package Industrial temperature range available Block Diagram The standard external clock feedback configuration is shown. Use this configuration for the pre-configured input/output frequency combinations listed above. C S C B R S CHGP CHPR Phase Charge Detector Pump 0 REFIN VS Clock Input MUX VCO CLK1 Divider 1 CLK2 300 pF CLK2 Divider 0 FBIN MUX Divider FCLK 1 FCLK LUT Divider 3 FS2:0 OE External Feedback Clock Connection IDT CLOCK RECOVERY PLL 1 MK1575-01 REV P 051310MK1575-01 CLOCK RECOVERY PLL CLOCK SYNTHESIZER Pin Assignment REFIN 1 16 FBIN FS0 2 15 NC VDDA 3 14 FCLK VDDD 4 13 OE FS1 5 12 CLK2 GNDA 6 11 FS2 GNDD 7 10 CLK1 CHGP 8 9 CHPR 16 pin 4.40 mil body, 0.65 mil pitch TSSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type Reference clock input. Connect the input clock to this pin. Can be 1 REFIN Input Rising or Falling edge triggered as per Detailed Mode Selection Table, page 3. Frequency Selection Input bit 0, selects internal divider values as per 2FS0 Input Detailed Mode Selection Table, page 3. 3 VDDA Power Power supply connection for internal VCO and other analog circuits. 4 VDDD Power Power supply connection for internal digital circuits and output buffers. Frequency Selection Input bit 1, selects internal divider values as per 5FS1 Input Detailed Mode Selection Table, page 3. 6 GNDA Ground Ground connection for internal VCO and other analog circuits. 7 GNDD Ground Ground connection for internal digital circuits and output buffers. 8 CHGP Loop filter connection, active node. 9 CHPR Loop filter connection, reference node. Do not connect to ground. 10 CLK1 Output Output clock 1. Frequency Selection Input bit 2, selects internal divider values as per 11 FS2 Input Detailed Mode Selection Table, page 3. 12 CLK2 Output Output clock 2. Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL 13 OE Input when high. Internal pull-up. Feedback clock output, connect to FBIN for the pre-configured 14 FCLK Output frequency combinations listed in the tables on page 1. 15 NC No internal connection, connect to ground. Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of 16 FBIN Input an external feedback divider, depending on application. Refer to document text for more information. IDT CLOCK RECOVERY PLL 2 MK1575-01 REV P 051310