DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description Features The MK2049-45 is a dual Phase-Locked Loop (PLL) device Packaged in 20 pin SOIC which can provide frequency synthesis and jitter 3.3 V + 5% operation attenuation. The first PLL is VCXO based and uses a Meets the TR62411, ETS300 011, and GR-1244 pullable crystal to track signal wander and attenuate input specification for MTIE, Pull-in/Hold-in Range, Phase jitter. The second PLL is a translator for frequency Transients, and Jitter Generation for Stratum 3, 4, and 4E multiplication. Basic configuration is determined by a Accepts multiple inputs: 8 kHz backplane clock, or 10 to Mode/Frequency Selection Table. Loop bandwidth and 50 MHz damping factor are programmable via external loop filter Locks to 8 kHz + 100 ppm (External mode) component selection. Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs Buffer Mode accepts a 10 to 50MHz input and will provide a Exact internal ratios enable zero ppm error jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal for filtering jitter from Output rates include T1, E1, T3, E3, and OC3 submultiples high frequency clocks. Available in Pb (lead) free package In External Mode, ICLK accepts an 8 kHz clock and will See also the MK2049-34 and MK2049-36 produce output frequencies from a table of common communciations clock rates, CLK and CLK/2. This allows Not recommended for new designs. Use the MK2049-45A. for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-45 can be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. ICS can customize these devices for many other different frequencies. Contact your ICS representative for more details. Block Diagram C S C C Optional Crystal Load Caps R L L SET C P R S External Pullable Crystal ISET CAP2 CAP1 X1 X2 Phase Detector Reference Divider Reference Output ICLK VCXO VCO CLK (used in buffer Divider Divider mode only) Charge Divide CLK/2 Pump by 2 Feedback Feedback Divider Divider (N) Translator VCXO PLL PLL 8k 4 Divider Value FS3:0 Look-up Table IDT / ICS 3.3 VOLT COMMUNICATIONS CLOCK PLL 1 MK2049-45 REV G 101904MK2049-45 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Pin Assignment FS1 1 20 FS0 X2 2 19 RES X1 3 18 CAP2 VDD 4 17 GND FCAP 5 16 CAP1 VDD 6 15 VDD GND 7 14 GND CLK 8 13 ICLK CLK/2 9 12 FS3 8k 10 11 FS2 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 2 X2 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2. 3 X1 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2. 4 VDD Power Power supply. Connect to +3.3V. 5 FCAP - Filter capacitor. Connect a 1000 pF ceramic capacitor to ground. 6 VDD Power Power supply. Connect to +3.3V. 7 GND Power Connect to ground 8 CLK Output Clock output determined by status of FS3:0 per tables on page 2. 9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of CLK. 10 8k Output Recovered 8 kHz clock output. 11 FS2 Input Frequency select 2. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 12 FS3 Input Frequency select 3. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND Power Connect to ground. 15 VDD Power Power Supply. Connect to +3.3V. 16 CAP1 Loop Connect the loop filter capacitors and resistor between this pin and CAP2. Filter 17 GND Power Connect to ground. IDT / ICS 3.3 VOLT COMMUNICATIONS CLOCK PLL 2 MK2049-45 REV G 101904