DATASHEET VCXO-BASED UNIVERSAL CLOCK TRANSLATOR MK2069-04 Description Features The MK2069-04 is a VCXO (Voltage Controlled Crystal Input clock frequency <1 kHz to 170 MHz Oscillator) based clock generator that features a PLL Output clock frequency of 500 kHz to 160 MHz (Phase-Locked Loop) input reference divider and feedback Clock translation examples: divider that have a wide numeric range selectable by the T1 (1.544 MHz) to/from E1 (2.048 MHz) user. This enables a complex PLL multiplication ratio that T3 (44.736 MHz) to/from E3 (34.368 MHz) can be used for translation between clock frequency standards. OC-3 (155.52 MHz) to/from T1 (1.544 MHz) CCIR-601 (27 MHz) to/from SMPTE 274M (74.125 The on-chip VCXO produces a stable, low jitter output clock MHz) using a phase detector frequency down to 8 kHz or lower. This means the MK2069-04 can translate between clock Jitter attenuation of input clock provided by VCXO circuit. Jitter transfer characteristics user configured through frequencies that have a low common denominator, such as external loop filter component selection. the 8 kHz frame clock common with telecom standards. The Low jitter and phase noise generation. MK2069-04 also provides jitter attenuation of the input clock and can accept a low input frequency as well. PLL lock status output PLL Clear function allows seamless synchronizing to an The device is optimized for user configurability by providing altered input clock phase access to all major PLL divider functions. No power-up 2nd PLL provides frequency translation of VCXO PLL programming is needed as configuration is pin selected. output (VCLK) to a higher or alternate output frequency External VCXO loop filter components provide an additional (TCLK). level of user configurability. Device will free-run in the absence of an input clock The MK2069-04 includes a lock detector (LD) output that based on VCXO frequency. serves as a clock status monitor. The clear (CLR) input 56-pin TSSOP package enables rapid synchronization to the phase of a newly Single 3.3 V power supply selected input clock. 5 V tolerant clock input Pb (lead) free package Block Diagram Pullable xtal RPV RV11:0 SV1:0 ST VDD 12 2 4 ISET LF LFR X1 X2 VCLK Phase OEV Detector RPV RV SV ST ICLK VCXO Divider VCO TCLK Divider Divider Divider 1, 8 2 to 4097 1,2,12,16 2, 16 Charge OET Pump FV Divider FT Divider 2 to 16, even only 1 to 4096 Translator VCXO PLL PLL RCLK Lock Detector OER LD CLR OEL 12 LDC LDR 3 4 FV11:0 FT2:0 GND IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 1 MK2069-04 REV J 051310MK2069-04 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Pin Assignment Input Selection Tables VCXO PLL Reference Pre-Divider Selection Table RV5 1 56 RPV RV6 2 55 SV1 RPV RPV Pre-Divider Ratio RV7 3 54 SV0 01 RV8 4 53 RV4 18 FT0 5 52 RV3 FT1 6 51 RV2 VCXO PLL Reference Divider Selection Table FT2 7 50 OEL RV11:0 RV Divider Notes RV9 8 49 OET Ratio RV10 9 48 OEV 0...00 2 RV11 10 47 OER RV Divide Value 0...01 3 = Address + 2 ST 11 46 VDD :: VDDT 12 45 LD 1...11 4097 GNDT 13 44 TCLK X1 14 43 VDDP VCXO PLL Feedback Divider Selection VDDV 15 42 VCLK FV11:0 FV Divider Ratio Notes X2 16 41 GNDP For FV addresses 0 to 4094, 0...00 2 GNDV 17 40 RCLK FV Divide Value 0...01 3 = Address + 2 LFR 18 39 LDR :: LF 19 38 GND 1...10 4096 ISET 20 37 LDC 1...11 1 FV0 21 36 CLR FV1 22 35 ICLK VCXO PLL Scaling Divider Selection Table FV2 23 34 RV1 SV1 SV0 SV Divider Ratio FV3 24 33 RV0 00 12 FV4 25 32 FV11 01 2 FV5 26 31 FV10 10 16 FV6 27 30 FV9 11 1 FV7 28 29 FV8 Translator PLL Feedback Divider Selection FT2 FT1 FT0 FT Divider Ratio 000 4 001 6 010 8 011 10 100 12 101 14 110 16 111 2 Translator PLL Scaling Divider Selection Table ST ST Divider Ratio 02 116 IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 2 MK2069-04 REV J 051310