MK2712 NTSC/PAL Clock Source Description Features Packaged in 8 pin SOIC The MK2712 is the ideal way to generate clocks for NTSC/PAL video encoders and decoders. Stored in Ideal for chips such as Analog Devices AD722 the device are two sets of popular frequencies for and Brooktree BT819 NTSC and PAL. In an 8 pin SOIC, the chip can save Input clock frequency of 27.0000 MHz component count, board space, and cost over surface mount crystals and oscillators, and increase reliability Power down turns off chip by eliminating one or two mechanical devices from the Output enable tri-states output for system testing board. The power down pin turns off the device, Frequencies are within 1 ppm with accurate drawing less than 20A. input clock ICS/MicroClock offers many other clocks for computers Low jitter and computer peripherals. Consult us when you need Output clock frequencies of 14.31818MHz, to remove crystals and oscillators from your board. 17.7345MHz, 28.6364MHz, or 35.46896MHz 25mA drive capability at TTL levels 3.3V or 5V supply voltage Advanced, low power CMOS process Insensitive to input clock duty cycle Block Diagram VDD GND 2 FS0, 1 PLL Output NTSC/PALCL Clock Synthesis PD Buffer OCK Circuitry 27.00 MHz clock input OE MDS 2712 D 1 Revision 092104 Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)297-1201tel www.icst.comMK2712 NTSC/PAL Clock Source Pin Assignment Decoding Table 1 8 FS0 FS1 FS0 NPCLK (MHz) Error (ppm) ICLK 0 0 14.31818 0.3 ppm 7 2 VDD PD 0 1 17.73447 0.3 ppm 1 0 28.63636 0.3 ppm 3 6 GND OE 1 1 35.46894 0.3 ppm 4 5 FS1 NPCLK 8 pin SOIC Pin Descriptions Number Name Type DescriptionDescription 1 ICLK I Input Clock. Connect to a 27.0000 MHz clock.Input Clock. Connect to a 27.0000 MHz clock. 2 VDD P Connect to +3.3V or +5V.Connect to +3.3V or +5V. 3 GND P Connect to ground.Connect to ground. 4 NPCLK O NTSC or PAL output clock. Selected by FS1, FS0 per tables above.NTSC or PAL output clock. Selected by FS1, FS0 per tables above. 5 FS1 I Frequency Select pin 1. Selects NTSC or PAL frequency per table above.Frequency Select pin 1. Selects NTSC or PAL frequency per table above. 6 OE I Output Enable. Tri-states clock output when this input is low. Internal pull-up.Output Enable. Tri-states clock output when this input is low. Internal pull-up. 7 PD I Power Down. Active low. Clocks stop low.Power Down. Active low. Clocks stop low. 8 FS0 I Frequency Select pin 0. Selects NTSC or PAL frequency per table above.Frequency Select pin 0. Selects NTSC or PAL frequency per table above. Key: I = Input, O = output, P = power supply connection External Components/Crystal Selection A minimum number of external components are required for proper oscillation. Connect a 27.000 MHz clock to ICLK. A decoupling capacitor of 0.1F should be connected between VDD and GND on pins 2 and 3, and a 33 terminating resistor should be used on the clock output if the trace is longer than 1 inch. MDS 2712 D 2 Revision 092104 Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408)297-1201tel www.icst.com