3.3V/2.5V 1:11 LVCMOS Zero Delay MPC9352 Clock Generator PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews lower than 200 ps, the device meets the needs of MPC9352 most demanding clock applications. Features Configurable 11 Outputs LVCMOS PLL Clock Generator Fully Integrated PLL LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:11 Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz CLOCK GENERATOR Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3 2, 2 3, 1 3 and 1 2 2.5 V and 3.3 V LVCMOS Compatible Maximum Output Skew of 200 ps Supports Zero-Delay Applications Designed for High-Performance Telecom, Networking and Computing Applications 32-Lead LQFP Package, Pb-Free AC SUFFIX 32-LEAD LQFP PACKAGE Ambient Temperature Range 40C to +85C Pb-FREE PACKAGE For functional replacement use 8T49N285 CASE 873A-03 The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and clock driver. The device has the capability to gen- erate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL is optimized for its frequency range and does not require external lock filter components. One output of the MPC9352 has to be connected to the PLL feedback input FB IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli- cation factor. This multiplication factor, F RANGE, and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different, but phase-aligned, clock frequencies. The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out- puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22. The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC9352 is packaged in a 32 ld LQFP. MPC9352 REVISION 8 MARCH 14, 2016 1 2016 Integrated Device Technology, Inc.MPC9353 Data Sheet 3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR Bank A CCLK QA0 1 2 1 6 1 CCLK QA1 Ref VCO 0 0 0 4 QA2 PLL FB IN FB QA3 2 QA4 PLL EN Bank B QB0 1 F RANGE QB1 0 FSELA QB2 QB3 FSELB Bank C 1 QC0 FSELC QC1 0 MR/OE (All input resistors have a value of 25 k) Figure 1. MPC9352 Logic Diagram 24 23 22 21 20 19 18 17 25 16 V V CC CC 26 15 QA2 QB2 27 14 QA1 QB3 28 13 GND GND MPC9352 29 12 QA0 GND 30 11 V QC0 CC 31 10 QC1 V CCA 32 9 V PLL EN CC 12 3 4 5 6 78 It is recommended to use an external RC filter for the analog power supply pin V . Please see Applications Information section for details. CCA Figure 2. MPC9352 32-Lead Package Pinout (Top View) MPC9352 REVISION 8 MARCH 14, 2016 2 2016 Integrated Device Technology, Inc. F RANGE GND FSELC QB1 FSELB QB0 FSELA V CC MR/OE V CC CCLK QA4 QA3 GND GND FB IN