Low Voltage, 1:27 Clock Distribution Chip MPC941 DATA SHEET The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 27 outputs are LVCMOS compatible and feature the drive strength to LOW VOLTAGE 3.3 V/2.5 V drive 50 series or parallel terminated transmission lines. With output-to-output 1:27 CLOCK skews of 250 ps, the MPC941 is ideal as a clock distribution chip for the most DISTRIBUTION CHIP demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet. LVPECL or LVCMOS Clock Input 250 ps Maximum Output-to-Output Skew Drives Up to 54 Independent Clock Lines Maximum Output Frequency of 250 MHz High Impedance Output Enable Extended Temperature Range: 40 C to +85C SCALE 2:1 48-Lead LQFP Packaging, Pb-free AE SUFFIX 3.3 V or 2.5 V V Supply Voltage CC 48-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 932-03 With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated 50 transmission lines. With this capability, the MPC941 has an effective fanout of 1:54. With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS CLK Sel pin will select the LVCMOS level clock input. The MPC941 is fully 3.3 V and 2.5 V compatible. The 48-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 48-lead LQFP has a 7x7 mm body size. MPC941 REVISION 10 3/18/15 1 2015 Integrated Device Technology, Inc.MPC941 DATA SHEET LOGIC DIAGRAM PECL CLK Pulldown 0 PECL CLK Q0 1 LVCMOS CLK Pulldown 25 Q1Q25 LVCMOS CLK SEL Pulldown Q26 OE PULLDOWN Pinout: 48-Lead TQFP (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 V 37 24 GND CC FUNCTION TABLE 38 23 Q7 Q16 LVCMOS CLK SEL Input 39 22 Q6 Q17 0 PECL CLK Q5 40 21 Q18 1 LVCMOS CLK 41 20 GND V CC Q4 42 19 Q19 MPC941 Q3 43 18 Q20 17 V 44 GND CC Q2 45 16 Q21 46 15 Q1 Q22 14 Q0 47 Q23 GND 48 13 V CC 1 2345 678 9 10 11 12 Table 1. Pin Configuration Pin I/O Type Function PECL CLK, Input LVPECL LVPECL differential reference clock inputs PECL CLK LVCMOS CLK Input LVCMOS Alternative reference clock input LVCMOS CLK SEL Input LVCMOS Input reference clock select OE Input LVCMOS Output tristate control GND Supply Negative voltage supply output bank (GND) V Supply Positive voltage supply CC Q0Q26 Output LVCMOS Clock outputs REVISION 10 3/18/15 2 LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP GND GND Q8 OE Q9 LVCMOS CLK LVCMOS CLKSEL Q10 V V CC CC PECL CLK Q11 PECL CLK Q12 V GND CC Q26 Q13 Q25 Q14 Q24 Q15 GND V CC