3.3V and 2.5V, LVCMOS Clock Fanout MPC9446
Buffer
DATA SHEET
The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed
for low-voltage mid-range to high-performance telecom, networking and computing
applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage
MPC9446
applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1 and 1:2 output to input
frequency ratios. The MPC9446 is specified for the extended temperature range of 40 C
to 85C.
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5 V AND 3.3 V
Features
LVCMOS CLOCK
Configurable 10 outputs LVCMOS clock distribution buffer
DISTRIBUTION BUFFER
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking
and computer applications
Supports applications requiring clock redundancy
Maximum output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
AC SUFFIX
Tristable outputs
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
32-lead LQFP package, Pb-free
CASE 873A-04
Ambient operating temperature range of 40 to 85 C
Functional Description
The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250
MHz. The signals are generated and retimed on-chip to ensure minimal skew between the
three output banks. Two independent LVCMOS compatible clock inputs are available. This
feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be
individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input refer-
ence frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be
pin (logic high state). Asserting MR/OE will enable the outputs.
rese,t and the outputs are disabled by deasserting the MR/OE
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series
terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20.
2
The device is packaged in a 7x7 mm 32-lead LQFP package.
MPC9446 REVISION 5 2/13/15 1 2015 Integrated Device Technology, Inc.MPC9446 DATA SHEET
V
CC
Bank A
25k
QA0
0 0
CCLK0
CLK
V
CC
QA1
25k
CCLK1 1 CLK 2 1
QA2
CCLK_SEL
25k
Bank B
QB0
0
QB1
1
QB2
QC0
Bank C
FSELA
0
QC1
25k
FSELB
QC2
1
25k
FSELC
QC3
25k
MR/OE
25k
Figure 1. MPC9446 Logic Diagram
V is internally connected to V
CCB CC
24 23 22 21 20 19 18 17
25 16 QC3
V
CCA
26 15 GND
QA2
27 14 QC2
GND
28 13 V
QA1
CCC
MPC9446
V 29 12 QC1
CCA
30 11 GND
QA0
31 10
GND QC0
32 9
MR/OE V
CCC
12 3 4 5 6 78
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
REVISION 5 2/13/15 2 3.3V AND 2.5V, LVCMOS CLOCK FANOUT BUFFER
CCLK_SEL GND
V QB0
CC
V
CCLK0
CCB
CCLK1 QB1
GND
FSELA
QB2
FSELB
V
FSELC CCB
V
GND CCC