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SEMICONDUCTOR TECHNICAL DATA
by MPC9600/D
!
The MPC9600 is a low voltage 2.5V and 3.3V compatible, 1:21 PLL
based clock driver and fanout buffer. With output frequencies up to 200
MHz, output skews of 150 ps and parttopart skews of 300 ps the device
meets the needs of the most demanding clock tree applications.
LOW VOLTAGE CMOS
Features:
Multiplication of input frequency by 2, 3, 4 and 6 PLL CLOCK DRIVER
Distribution of output frequency to 21 outputs organized in three output
banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable
Fully integrated PLL
Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz
Selectable input frequency range is 16 to 33 MHz and 25 to 50 MHz
LVCMOS outputs
Outputs disable to high impedance (except QFB)
LVCMOS or LVPECL reference clock options
48 lead QFP packaging
50 ps cycle-to-cycle jitter
150 ps maximum output-to-output skew
300 ps maximum device-to-device skew
FA SUFFIX
48LEAD LQFP PACKAGE
CASE 93203
The MPC9600 is fully 2.5V and 3.3V compatible. The MPC9600 has the
capability to generate clock signals of 50 to 200 MHz from clock sources of
16 to 50 MHz. The internal PLL is optimized for this frequency range and
does not require external loop filter components. QFB provides an output for
the external feedback path to the feedback input FB_IN. The QFB divider
ratio is configurable and determines the PLL frequency multiplication factor
when QFB is directly connected to FB_IN. The MPC9600 is optimized for
minimizing the propagation delay between the clock input and FB_IN.
Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining
the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6.
The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use
LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels.
The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to V =V /2. For
TT CC
series terminated lines the MPC9600 can drive two lines per output giving the device and effective total fanout of 1:42. With
guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of
the most demanding systems.
The V analog power pin doubles as a PLL bypass select line for test purpose. When the V is driven to GND the reference
CCA CCA
clock will bypass the PLL and will drive the outputs (except QFB) into a high impedance state.
The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
06/00
REV 0
Motorola, Inc. 2000 1VCCA VCC
7
(pulldown)
0
TCLK 0
Bank A
QA0
/2 0
PLL
Ref
(pulldn)
PCLK
1
D Q QA1
1
/4
PCLK
1
FB
/8
Vcc/2 QA2
(pullup) 200 - 400 MHz
REF_SEL /12
QA3
(pulldown)
FB_IN
QA4
(pullup)
FSELA
QA5
QA6
Bank B
0
D Q QB0-6
7
1
(pullup)
FSELB
Bank C
0
D Q QC0-6
7
1
(pullup)
FSELC
Feedback
0
D Q QFB
1
(pullup)
FSEL_FB
(pulldown)
OE
8
GND
Figure 1. MPC9600 Logic Diagram
PIN CONFIGURATION
Pin I/O Type Description
PCLK, PCLK Input PECL Differential reference clock frequency input
TCLK Input LVCMOS Reference clock input
FB_IN Input LVCMOS PLL feedback clock input
QAn Output LVCMOS Bank A outputs
QBn Output LVCMOS Bank B outputs
QCn Output LVCMOS Bank C outputs
QFB Output LVCMOS Differential feedback output
REF_SEL Input LVCMOS Reference clock input select
FSELA Input LVCMOS Selection of bank A output frequency
FSELB Input LVCMOS Selection of bank B output frequency
FSELC Input LVCMOS Selection of bank C output frequency
FSEL_FB Input LVCMOS Selection of feedback frequency
OE Input LVCMOS Output enable
VCCA Power supply Analog power supply and PLL bypass
VCC Power supply Core power supply
GND Ground Ground
Motorola 2