SLG59H1010V SLG59H1010V A 13.3 m, 5 A Integrated Power Switch with 12 V / 24 V V Lockout Select and MOSFET Current Monitor Output IN General Description Pin Configuration RSET IOUT The SLG59H1010V is a high-performance 13.3 m NMOS power switch designed to control 12 V or 24 V power rails up 1 ON 16 CAP to 5 A. Using a proprietary MOSFET design, the 18 17 SLG59H1010V achieves a stable 13.3 m RDS across a ON GND 2 15 FAULT wide input voltage range. In combining novel FET design and copper pillar interconnects, the SLG59H1010V package also GND 3 14 SEL exhibits a low thermal resistance for high-current operation. VIN 4 13 VOUT Designed to operate over a -40 C to 85 C range, the VIN 5 12 VOUT SLG59H1010V is available in a low thermal resistance, RoHS-compliant, 1.6 x 3.0 mm STQFN package. VIN 6 11 VOUT 10 VIN 7 89 VOUT Features Wide Operating Input Voltage: 12 V or 24 V VIN VOUT Maximum Continuous Current: 5 A Automatic nFET SOA Protection 18-pin STQFN High-performance MOSFET Switch 1.6 x 3.0 mm, 0.40mm pitch Low RDS : 13.3 m at V = 24 V ON IN (Top View) Low RDS /V : < 0.05 m/V ON IN Low RDS /T: < 0.06 m/C ON Pin-selectable 12V/24V Input Overvoltage Applications and Undervoltage Lockout Power-Rail Switching Capacitor-adjustable Inrush Current Control Multifunction Printers Two stage Current Limit Protection: Large-format Copiers Resistor-adjustable Active Current Limit Telecommunications Equipment Internal Short-circuit Current limit High-performance Computing Open Drain FAULT Signaling 12 V and 24 V Point-of-Load Power Distribution MOSFET Current Analog Output Monitor: 10 A/A Motor Drives Fast 4 k Output Discharge Pb-Free / Halogen-Free / RoHS Compliant Packaging Block Diagram and 3 A Typical Application Circuit 24 V 5% C = C + C 3 A VOUT LOAD 5 6 VIN C = C + C + C IN 1 2 3 C C 5 6 47 F 22 F Charge C C C 1 2 3 Pump 47 F 22 F 0.1 F 3 V FS - Connect to System ADC IOUT Linear Ramp Control CAP C R IOUT IOUT C SLEW 180 pF RSET 84.5 k 10 nF V LOGIC R SET V State Machine LOGIC 30.1 k R (CL/SC Detection and PU 10 k Over Temperature R PU SEL 27 V OVLO Protection) 100 k 20.5 V UVLO 24 V V IN Lockout Selected Connect to FAULT ON System GPI ON CMOS Input Discharge OFF GND Datasheet Revision 1.02 12-Dec-2018 Page 1 of 31 2018 Dialog Semiconductor CFR0011-120-01SLG59H1010V A 13.3 m, 5 A Integrated Power Switch with 12 V / 24 V V Lockout Select and MOSFET Current Monitor Output IN Pin Description Pin Pin Name Type Pin Description A low-to-high transition on this pin initiates the operation of the SLG59H1010Vs state machine. ON is an asserted HIGH, level-sensitive CMOS input with ON V < 0.3 V and ON V > 0.9 V. As IL IH 1 ON Input the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller, do not allow this pin to be open-circuited. 2GND GND Pin 2 is a low-current GND terminal for the SLG59H1010V. Connect directly to Pin 3. Pin 3 is the main ground connection for the SLG59H1010Vs internal charge pump, its gate driver 3GND GND and current-limit circuits as well as its internal state machine. Therefore, use a short, stout connection from Pin 3 to the systems analog or power plane. VIN supplies the power for the operation of the SLG59H1010V, its internal control circuitry, and the drain terminal of the nFET power switch. With 5 pins fused together at VIN, connect a 47 F (or 4-8 VIN MOSFET larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 50 V or higher. Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 47 F (or larger) 9-13 VOUT MOSFET low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 50 V or higher. As a low logic-level CMOS input with SEL V < 0.3 V and SEL V > 1.65 V, SEL selects one of IL IH two undervoltage/overvoltage lockout windows. When SEL = LOW, the V IN 14 SEL Input undervoltage/overvoltage lockout window is set for 12 V 10% applications. When SEL = HIGH, the V undervoltage/overvoltage lockout window is set for 24 V 5% applications. See the IN Electrical Characteristics table for additional information. An open drain output, FAULT is asserted within TFAULT when a V undervoltage, V LOW IN IN overvoltage, a current-limit, or an over-temperature condition is detected. FAULT is deasserted 15 FAULT Output within TFAULT when the fault condition is removed. Connect an 100 k external resistor from HIGH the FAULT pin to local system logic supply. A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the V slew rate and overall turn-on time of the SLG59H1010V. For best performance, the OUT 16 CAP Output range for C values are 10 nF C 20 nF please see typical characteristics for additional SLEW SLEW information. Capacitors used at the CAP pin should be rated at 10 V or higher. Please consult Applications Section on how to select C based on V slew rate and loading conditions. SLEW OUT IOUT is the SLG59H1010Vs power MOSFET load current monitor output. As an analog current output, this signal when applied to a ground-reference resistor generates a voltage proportional to the current through the n-channel MOSFET. The I transfer characteristic is typically 10 A/A OUT 17 IOUT Output with a voltage compliance range of 0.5 V V 4 V. Optimal I linearity is exhibited for IOUT OUT 0.5 A I 5 A. In addition, it is recommended to bypass the IOUT pin to GND with a 0.18 nF DS capacitor. A 1%-tolerance, metal-film resistor between 18 k and 91 k sets the SLG59H1010Vs active 18 RSET Input current limit. A 91 k resistor sets the SLG59H1010Vs active current limit to 1 A and a 18 k resistor sets the active current limit to 5 A. Ordering Information Part Number Type Production Flow SLG59H1010V STQFN 18L FC Industrial, -40 C to 85 C SLG59H1010VTR STQFN 18L FC (Tape and Reel) Industrial, -40 C to 85 C Datasheet Revision 1.02 12-Dec-2018 Page 2 of 31 2018 Dialog Semiconductor CFR0011-120-01