Si5040 10 Gbps XFP TRANSCEIVER WITH JITTER ATTENUATOR Features Complete, high-performance, low-power, 10Gbps XFP transceiver featuring independent CDRs, DSPLL -based jitter-attenuating CMUs, and data retimers in both Si5100 transmit and receive directions. Transmitter jitter generation 2.5 mUI DSPLL-based, jitter-attenuating CMUs rms in both transmit and receive directions (typical) Frequency-agile jitter filtering from 9.8 to Automatic slicing level adjustment with 11.35 Gbps (continuous) optional programmable override Compliant to XFP specifications and Programmable sample phase jitter specifications for telecom adjustment (SONET/SDH, OTU-2) and datacom Line loopback, XFI loopback, pattern (10 GbE/10 GbE+FEC and generation, and pattern check test Ordering Information: 10 GFC/10 GFC+FEC) applications capabilities Supports referenceless operation 1.8/3.3 V or single 1.8 V supply See page 103. Integrated limiting amplifier provides 575 mW (typ) power dissipation better than 8 mV receiver sensitivity 5x5 mm LGA package User-programmable receiver loss-of- Serial microcontroller interface control signal (LOS) detector Pin Assignments Applications Si5040 (Transparent Top View) XFP telecom modules Jitter-attenuation and signal XFP datacom modules regeneration of 10 Gbps serial signal Optical test equipment on line cards 32 31 30 29 28 27 26 25 GND 1 24 SCK Description RX LOL 2 23 GND GND GND RX LOS 3 22 PAD PAD TD+ The Si5040 is a complete, low-power, high-performance XFP transceiver suitable for VDDIO 4 21 TD 5 20 GND multiple XFP module types, from short-reach datacom to long-reach telecom GND GND GND 6 19 RD+ RXDIN applications. The Si5040 integrates a rate-agile, programmable-bandwidth, jitter- PAD PAD RXDIN+ 7 18 RD attenuating CMU in the transmit direction, which significantly attenuates jitter present at GND 8 17 GND the XFI interface and on the applied reference clock, removing the need for an external 9 10 11 12 13 14 15 16 jitter cleanup circuit. The device supports referenceless operation or operation with a synchronous or asynchronous reference clock. The device can be completely configured through a serial microcontroller interface. The Si5040 is compliant with all XFP requirements in both datacom and telecom applications. The Si5040 is packaged in a 5x5 mm LGA package and dissipates 575 mW (typ). Functional Block Diagram RX LOS RX LOL Program D CDR CML RXDIN mable LA RD FIFO Clk Equalizer TM Control Interrupt DSPLL Jitter Attenuator XFI Line Loopback RefCLK Loopback (optional) TM DSPLL Serial Jitter Attenuator Serial Port Interface Clk D CDR Equalizer TXDOUT CML TD FIFO Rev. 1.3 6/12 Copyright 2012 by Silicon Laboratories Si5040 V SPSEL DD GND NC TXDOUT+ NC V TXDOUT DD REFCLK+ GND REFCLK- V DD V SS DD SD INTERRUPTSi5040 2 Rev. 1.3