Si50x-32x4-EVB EVALUATION BOARD FOR THE Si50X 3.2X4.0 MM SILICON OSCILLATORS Si50x samples should be ordered at the same time as Description the Si50x-32x4-EVB since the EVB does not come with This document describes the operation of the Silicon the device. This allows end users maximum flexibility. Laboratories Si50x-32x4-EVB Rev 2.0 evaluation board Silicon Laboratories can solder down samples when to evaluate Silicon Laboratories Si50x Silicon ordering an EVB please specify when ordering. Oscillators in the 3.2x4.0mm package. Devices currently available include the single-ended output Features Si500S and the differential output Si500D. The Si50x utilizes Silicon Laboratories ultra stable silicon oscillator Evaluation of Silicon Laboratories Si50x devices technology to achieve an inexpensive low jitter clock Stuffing options support dc or ac coupled single- source. This unique oscillator technology is factory ended or differential output clocks programmed to support any frequency between Supports output signal formats: CMOS, HCSL, Low 900kHz and 200MHz. Unlike traditional XOs that Power LVPECL, LVDS, LVPECL, or SSTL require a unique quartz crystal resonator to generate Jumper selections for OE and MODE (reserved for each frequency, the Si50x uses programmable, future use) compensated silicon oscillator architecture that is capable of operating over a wide range of output frequencies. In addition, Silicon Lab s compensated silicon oscillator provides stability comparable to fixed frequency crystal based oscillators. The Si50x is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, output drive strength, and OE behavior. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram Power Input CLK+ Configuration Output DC Si50x Jumpers Bias Block Device CLK- Rev. 0.2 10/08 Copyright 2008 by Silicon Laboratories Si50x-32x4-EVBSi50x-32x4-EVB 1.3. Preparing the EVB 1. Functional Description By default, the evaluation board is set up to support ac- The Si50x-32x4-EVB provides access to all I/O signals coupling of differential mode configured devices (i.e., for configuring, operating, and testing the device. Low Power LVPECL, LVDS, and SSTL). The stuffing Jumpers and test points are provided as described variations for the supported output modes are tabulated below. in Table 1. 1.1. Power Supply Table 1. Stuffing Variations The Si50x supports operation from nominal voltages of 1.8, 2.5, and 3.3 V. Supply VDD and GND are wired in Driver R1, R4 C2, C3 J2, J4 Instrument at the J1 terminals. Review the device data sheet and Termination part number for allowed configurations of output buffer CMOS empty empty empty Active scope type and device power supply. * probes 1.2. Jumpers HCSL empty 0.1 F filled HI-Z The jumpers at JP1 and JP2 allow one to pull up or pull Low Power empty 0.1 F filled 50 down OE or MODE to VDD or GND. (The MODE signal LVPECL is reserved for future use. It is not used by either the LVDS empty 0.1 F filled 50 Si500S or the Si500D.) The current silkscreen for these jumpers is reproduced in Figure 1. LVPECL 2.5 V 100 0.1 F filled 50 LVPECL 3.3 V 200 0.1 F filled 50 SSTL empty 0.1 F filled 50 *Note: Use of Coax and 50 termination produces good signal integrity but incorrect signal levels and power use of Coax and Hi-Z produces extremely bad signal integrity. Figure 1. Jumpers Silkscreen 1.3.1. LVPECL Biasing Pins 1 and 2 in Figure 1 refer respectively to the Si50x s Because the Si50x can support an LVPECL buffer type OE and MODE pins. The jumper positions are (in addition to CMOS, HCSL, LVDS, or SSTL), pulldown illustrated in Figure 2. resistor locations (R1 and R4) are available for proper The Si50x can be ordered with the OE pin pulled to the output biasing. For LVPECL buffers, correct biasing can desired state, so the JP1 jumper would typically be be achieved through a variety of equivalent circuits the needed only to access the opposing state. Si50x-32x4-EVB allows for a commonly used approximation using pulldown resistors. After the output biasing, the high-speed outputs are dc-blocked for connection to differently biased inputs such as standard test equipment. JP1, Force OE high 1.4. Test Points There are 4 through-hole test points as follows: TP1VDD JP1, Force OE low TP2Output CLK N TP3GND TP4Output CLK JP2, Force Mode high Test point TP1 is located near terminal J1. Test points TP2TP4 are located in between the output connectors. JP2, Force Mode low Figure 2. JP1JP2 Jumper Positions 2 Rev. 0.2