Si5335 WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER Features Low power MultiSynth technology Independent output voltage per driver: enables independent, any-frequency 1.5, 1.8, 2.5, or 3.3 V synthesis of four frequencies Single supply core with excellent Configurable as a clock generator or PSRR: 1.8, 2.5, 3.3 V clock buffer device Up to five user-assignable pin Three independent, user-assignable, pin- functions simplify system design: selectable device configurations SSENB (spread spectrum control), Highly-configurable output drivers with RESET, Master OEB or OEB per pin, up to four differential outputs, eight and Frequency plan select single-ended clock outputs, or a (FS1, FS0) Ordering Information: combination of both Loss of signal alarm See page 41. Low phase jitter of 0.7 ps RMS PCIe Gen 1/2/3/4 common clock Flexible input reference: compliant External crystal: 25 or 27 MHz PCIe Gen 3 SRNS Compliant CMOS input: 10 to 200 MHz Two selectable loop bandwidth Pin Assignments SSTL/HSTL input: 10 to 350 MHz settings: 1.6 MHz or 475 kHz Differential input: 10 to 350 MHz Easy to customize with web-based Independently configurable outputs utility Top View support any frequency or format: Small size: 4 x 4 mm, 24-QFN LVPECL/LVDS/CML: 1 to 350 MHz Low power (core): HCSL: 1 to 250 MHz 45 mA (PLL mode) CMOS: 1 to 200 MHz 12 mA (Buffer mode) 24 23 22 21 20 19 SSTL/HSTL: 1 to 350 MHz XA/CLKIN 1 18 CLK1A Wide temperature range: 40 to +85 C XB/CLKINB 2 17 CLK1B 3 16 P3 VDDO1 Applications GND GND Pad GND 4 15 VDDO2 Ethernet switch/router Processor and FPGA clocking 5 P5 14 CLK2A PCI Express Gen 1/2/3/4 MSAN/DSLAM/PON 6 13 P6 CLK2B PCIe jitter attenuation Fibre Channel, SAN 7 8 9 10 11 12 DSL jitter attenuation Telecom line cards Broadcast video/audio timing 1 GbE and 10 GbE Description The Si5335 is a highly flexible clock generator capable of synthesizing four completely non-integer-related frequencies up to 350 MHz. The device has four banks of outputs with each bank supporting one differential pair or two single-ended outputs. Using Silicon Laboratories patented MultiSynth fractional divider technology, all outputs are guaranteed to have 0ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ICs and crystal oscillators with a single device. The Si5335 supports up to three independent, pin-selectable device configurations, enabling one device to replace three separate clock generators or buffer ICs. To ease system design, up to five user-assignable and pin-selectable control pins are provided, supporting PCIe-compliant spread spectrum control, master and/or individual output enables, frequency plan selection, and device reset. Two selectable PLL loop bandwidths support jitter attenuation in applications, such as PCIe and DSL. Through its flexible ClockBuilder (www.silabs.com/ClockBuilder) web configuration utility, factory-customized, pin-controlled devices are available in two weeks without minimum order quantity restrictions. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Rev. 1.4 12/15 Copyright 2015 by Silicon Laboratories Si5335 VDD VDD LOS RSVD GND CLK3B CLK0A CLK3A CLK0B VDDO3 VDDO0 P1 P2Si5335 Functional Block Diagram Osc VDDO0 PLL Bypass CLK0A MultiSynth0 XA / CLKIN CLK0B XB / CLKINB PLL PLL Bypass OEB0 VDDO1 CLKIN CLK1A MultiSynth1 CLK1B Programmable OEB1 PLL Bypass VDDO2 Pin Function P1 Options: CLK2A P2 MultiSynth2 P3 CLK2B OEB0/1/2/3 Control P5 OEB all OEB2 PLL Bypass P6 SSENB VDDO3 FS 1:0 CLK3A RESET MultiSynth3 CLK3B LOS OEB3 2 Rev. 1.4