M40SZ100WMQ6F STMicroelectronics

M40SZ100W 3 V NVRAM supervisor for LPSRAM Datasheet - production data Description The M40SZ100W NVRAM controller is a self- 16 contained device which converts a standard low- power SRAM into a non-volatile memory. A 1 precision voltage reference and comparator monitors the V input for an out-of-tolerance CC condition. SO16 When an invalid V condition occurs, the CC conditioned chip enable output (E is forced CON) inactive to write protect the stored data in the Features SRAM. During a power failure, the SRAM is switched from the V pin to the external battery CC Convert low power SRAMs into NVRAMs to provide the energy required for data retention. 3 V operating voltage On a subsequent power-up, the SRAM remains write-protected until a valid power condition Precision power monitoring and power returns. switching circuitry Automatic write-protection when V is out-of- CC tolerance Choice of supply voltage and power-fail deselect voltage: V = 2.7 to 3.6 V 2.55 V V 2.70 V CC PFD Reset output (RST) for power on reset 1.25 V reference (for PFI/PFO) Less than 15 ns chip enable access propagation delay Battery low pin (BL) RoHS compliant Lead-free second level interconnect December 2013 DocID007528 Rev 4 1/20 This is information on a product in full production. www.st.comContents M40SZ100W Contents 1 Device overview 5 2 Operation 8 2.1 Data retention lifetime calculation . 8 2.2 Power-on reset output . 11 2.3 Reset input (RSTIN) . 11 2.4 Battery low pin . 11 2.5 Power-fail input/output . 12 2.6 V noise and negative going transients . 12 CC 3 Maximum ratings . 14 4 DC and AC parameters 15 5 Package mechanical data 17 6 Part numbering 18 7 Revision history . 19 2/20 DocID007528 Rev 4