STA2062 Cartesio family Infotainment application processor with embedded GPS Data Brief Features High performance ARM926 MCU (up to 333 MHz) MCU memory organization Cache: 16 KByte instruction, 16 KByte data 8 KByte instruction TCM (tightly coupled memory) LFBGA361 (16x16x1.4mm) 8 KByte data TCM 32 KByte embedded ROM for boot Motorola-SPI, National-MicroWire and Texas- SSI support modes Two banks of 64 KByte embedded SRAM Four multichannel serial ports (MSP) with 32x8 512 Byte embedded SRAM for back-up separate transmit and receive FIFO 4 GByte total linear address space Color LCD controller for STN,TFT or HR-TFT Memory extension through: panels Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM USB 2.0 OTG high speed dual role controller support) (ULPI interface) Mobile DDR/SDRAM controller: USB full speed dual role controller with 16 bit data 166 MHz, 2 Chip Select, integrated 1.1 physical layer transceiver 512 Kbit each Two secure-digital multimedia memory card Interrupt Interface (SD/SDIO/MMC) up to 8 bit data 64-channel interrupt controller (VIC) SPDIF input interface 16-vectorized interrupts with 16 C3 hardware Reed-Solomon decoder programmable priority Level Hardware sample rate converter (SaRaC) DMA Four 32-bit GPIO ports Two 8-channel double port system DMA JTAG based in-circuit emulator (ICE) with controllers embedded medium trace module 32 DMA request for each controller Typical working condition: V : 1.2 10% V, dd Two external DMA requests are supported V : 1.8 V IO 32 channel high performance GPS correlation Overdrive: V : 1.4 V 5 %, V : 1.8 V 10 %, dd IO embedded subsystem 2.5 V 10 % Eight 32-bit free running timers/counters Bus frequency: 166 MHz (overdrive) Four 16-bit extended function timer (EFT) with Bus/DDR frequency: 166 MHz input capture/output compare and PWM HCMOS 0.90m process Real time clock (RTC) Package: Pulse width light modulator (PWL) LFBGA16x16x1.4 mm (19x19balls) 32-bit watchdog timer 0.8 mm ball pitch, (0.4 mm ball) Four autobaud UART with 64X8 transmit and Full array 64x12 receive FIFO with DMA and hardware Ambient temperature range: -40 / +85 C flow control One IrDA(SIR/MIR/FIR) interface Table 1. Device summary 2 Three I C multi-master/slave interfaces Order code Package Packing Two synchronous serial port (SSP) with 32x32 separate transmit and receive FIFO with STA2062 LFBGA361 Tray September 2013 Rev 4 1/5 For further information contact your local STMicroelectronics sales office. www.st.com 5Description STA2062 1 Description The STA2062 is an highly integrated SOC application processor combining host capability with embedded GPS. STA2062 targets in vehicle and mobile navigation (PND), telematics, advance audio and connectivity systems. Figure 1: Block diagram gives an overview of the complete processor, showing how the ARM926 microcontroller and its peripherals are interfaced. Figure 1. Block diagram APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F APB I/F PORT FSMC PORT SDMC 2/5 DACK0 DREQ0 DACK1 DREQ1 TEST PORT ETM (JTAG) USB PHY DMA 1 DMA 0 M0 M1 S M1 S M0 ULPI Interface JTAG LCDC Interface ADDRESS 16 KB I / 16KB DCACHE CTRL FSMC S LCD CTRL USB OTG DATA eROM 8K ITCM / 8K DTCM USB FS S ARM926EJ VIC HS (8K x 32) IM DM S S S S M ARM AHB Instruction ARM AHB Data ADDRESS DMA 0 M0 CTRL eSRAM S S LCD AHB (32K x 32) DATA DMA 0/1 M1 SDMC DMA1 M0 S BACKUP AHB / APB S PLL1 Core Peripheral AHB / APB Bridge Audio & Automotive RAM S MXTAL S Bridge PLL2 (128 x 32) AHB / APB SRC DMA S Bridge SXTAL PWL AHB / APB GPS Bridge PWLOUT GPIO(0,3) BACKUP FIRRXD ARM HPGPS RTT IrDA (FIR/MIR/SIR) FIRTXD RTC WDT I2CSDAx ECLK0-3 Memory I2C(0,1,2) ARM7TMIS ,EFT I2CSCLx EFT(0,3) ICAPxA/ICAPxB PMU EIC MCCMD UTXDx OCMPxA/OCMPxB MCCMDDIR URTSxn MCCLK UDTR0n SPDIFIN SPDIF MCFBCLK WDT UART(0,3) URXD0 SD/SDIO/MMC(0,1) Emerald MCDIR0 UCTSxn X RAM Y RAM P RAM (12K x 16) DSP MCDIR2 UDCD0n C3 (8K x 16) (8K x 32) MCDIR31 UDSR0n MTU(0,1) URI0n MCDIR74 MCDAT 7:0 CHITF UUID SSPTXDx Support 32-Channels BD CLK2 Acquisition SSPTXDx CLK2 GPS Correlator Memory SSP(0,1) APB SSPCLKx CLK16 SSPFRMx SaRaC MSPTXDx HPGPS Interface MSPTFSx CORE IOs PLL MSPTCKx MSPRCKx MSP(0,1,2,3) MSPRFSx SUPPLY MSPSCKx MSPRXDx VDD VDD VDD 12 33 PLL MCU APB MXTAL GPSCLK uC2 APB