TB67S102AFNG,EL Toshiba

TB67S102AFG/FTG/FNG TOSHIBA BiCD Integrated Circuit Silicon Monolithic TB67S102AFG, TB67S102AFTG, TB67S102AFNG CLOCK-in controlled Bipolar Stepping Motor Driver The TB67S102A is a two-phase bipolar stepping motor driver FG using a PWM chopper. The clock in decoder is built in. Fabricated with the BiCD process, rating is 50 V/4.0 A . Features BiCD process integrated monolithic IC. HSOP28-P-0450-0.80 Capable of controlling 1 bipolar stepping motor. Weight 0.79g (Typ.) PWM controlled constant-current drive. Allows full, half, quarter step operation. Low on-resistance (High + Low side=0.49 (typ)) MOSFET output stage. FTG High efficiency motor current control mechanism (Advanced Dynamic Mixed Decay) High voltage and current (For specification, please refer to absolute maximum ratings and operation ranges) Built-in error detection circuits (Thermal shutdown (TSD), over-current shutdown (ISD), and power-on reset (POR)) P-WQFN48-0707-0.50-003 Built-in VCC regulator for internal circuit use. Weight 0.10g(Typ.) Chopping frequency of a motor can be customized by external resistance and condenser. Multi package lineup FNG TB67S102AFG: HSOP28-P-0450-0.80 TB67S102AFTG: P-WQFN48-0707-0.50-003 TB67S102AFNG: HTSSOP48-P-300-0.50 Note) Please be careful about thermal conditions during use. HTSSOP48-P-300-0.50 Weight 0.21g (Typ.) 2013-11-05 1 TB67S102AFG/FTG/FNG Pin assignment (TB67S102A) (Top View) CW/CCW 1 28 OSCM 27 VREFA MO 2 26 3 VREFB DMODE1 4 DMODE2 25 NC NC CLK 5 24 VCC ENABLE 6 23 22 VM RESET 7 FIN(GND) FIN(GND) FG RSA 8 21 RSB NC 9 20 NC OUTA+ 19 10 OUTB+ 11 18 NC NC 12 17 GND GND 13 OUTA- 16 OUTB- 14 GND 15 GND Please mount the FIN of the HSOP package to the GND area of the PCB. (Top View) 34 31 28 36 33 32 30 29 27 26 25 35 24 NC 37 NC 23 NC NC 38 22 GND NC 39 21 OUTB- 40 GND 20 OUTB- VREFB 41 FTG 19 GND 42 VREFA 18 GND 43 OSCM 17 OUTA- 44 CW/CCW 16 OUTA- MO 45 15 GND 46 DMODE1 14 NC DMODE2 47 13 NC 48 NC 3 6 9 12 1 2 4 5 7 8 10 11 Please mount the four corner pins of the QFN package and the exposed pad to the GND area of the PCB. 2013-11-05 2 NC NC CLK NC ENABLE VCC RESET NC GND VM NC NC RSA RSB RSA RSB NC NC OUTA+ OUTB+ OUTA+ OUTB+ NC NC