TC358867XBG CMOS Digital Integrated Circuit Silicon Monolithic TC358867XBG Mobile Peripheral Devices TC358867XBG Overview TC358867XBG is a bridge device that enables video streaming from a Host (application or baseband processor) over MIPI DSI or DPI link TM to drive DisplayPort display panels. TC358867XBG also supports audio streaming from the host via I2S interface to the Display panels. P-VFBGA80-0707-0.65-001 TC358867XBG provides a low power bridge solution to efficiently Weight: 76mg (Typ.) TM translate MIPI DSI or DPI transfers to DisplayPort transfers. As the TM DisplayPort uses fewer wires compared to other existing display panel standards, it simplifies the LCD connectivity. The effect of using TC358867XBG is to enable existing baseband devices supporting DSI or TM DPI streaming to connect to new panels supporting DisplayPort interface and also to connect to existing TM panels over longer distance using DisplayPort adaptors at far-end. Features Translates MIPI DSI/DPI Link video stream TM from Host to DisplayPort Link data to external Supports generic long packets for accessing display devices. the chips register set. Video input data formats: The inputs are driven by a DSI Host with 4-Data - RGB-565, RGB-666 and RGB-888. Lanes, upto1 Gbps/lane or DPI Host with - New DSI V1.02 Data Type Support: 16-bit 16/18/24 bit interface upto154 MHz parallel YCbCr 422 clock. Interlaced video mode is not supported. (Optional) Supports HDCP Digital Content TM Protection version 1.3 (DisplayPort DPI Receiver amendment Rev1.1). Up to 16 / 18 / 24 bit parallel data interface. Maximum speed at 154 MPs (Mpixel per sec). Embeds audio information from the I2S port into TM Video input data formats: RGB-565, RGB-666 the DisplayPort data stream. and RGB-888. TM The output Interface consists of a DisplayPort Only Progressive mode supported. Tx with a 2-lane Main Link and AUX-Ch. 2 I2S Audio Interface: Supports one I2S port for Register Configuration: From DSI link or I C audio streaming from the host to interface. TC358867XBG. Interrupt to host to inform any error status or Supports slave mode (BCLK, LRCLK & over- status needing attention from Host. sampling clock input from Host). Internal test pattern (color bar) generator for DP Supports sampling frequencies of 32, 44.1, 48, o/p testing without any video (DSI/DPI) i/p. 88.2, 96, 176.4 & 192 kHz. 2 Debug/Test Port: I C Slave Supports up to 2 audio channels. Supports 16, 18, 20 or 24bits per sample. DSI Receiver Optionally inserts IEC60958 status bits and MIPI DSI: v1.01 / MIPI D-PHY: v0.90 preamble bits per channel. Compliant. TM Up to four (4) Data Lanes with Bi-direction DisplayPort Interface: Supports a TM support on Data Lane 0. DisplayPort link from TC358867XBG to Maximum speed at 1 Gbps/lane. display panels. Supports Burst as well as Non-Burst Mode High speed serial bridge chip using VESA TM Video Data. DisplayPort 1.1a Standard. TM - Video data packets are limited to one row per Supports one dual-lane DisplayPort port for Hsync period. high bandwidth applications Supports video stream packets for video data Support 1.62 or 2.7 Gbps/lane data rate with transmission. voltage swings 0.4, 0.6, 0.8 or 1.2 V Support of pre-emphasis levels of 0, 3.5dB and 6dB. 2018 1 / 20 2018-05-28 Toshiba Electronic Devices & Storage Corporation Rev.1.1 TC358867XBG Clock Source: TM Supports Audio related Secondary Data DisplayPort clock source is from an external Packets. clock input or clock from DSI interface (13, 26, AUX channel supported at 1 Mbps. 19.2 or 38.4 MHz) generates all internal & HPD support through GPIO based interrupts output clocks to interfacing display devices. Enhanced mode supported for content Built-in PLLs generate high-speed TM protection. DisplayPort link clock requiring no external (Optional) Support HDCP encryption Version components. These PLLs are part of the TM TM 1.3 with DisplayPort amendment Revision DisplayPort PHY. 1.1. Clock and power management support to Secure ASSR (Alternate Scrambler Seed achieve low power states. Reset) support. Stream Policy Maker is assumed handled by Possible modes of Operation: TM the Host (software/firmware). MODE S21: TC358867XBG uses DisplayPort TM - Start Link training in response to HPD & read Tx as single 2-lane DisplayPort link to TM final Link training status interface to single DisplayPort display device. - Configure DP link for actual video streaming & Video stream source is from MIPI DSI Host. TM start video streaming MODE P21: TC358867XBG uses DisplayPort TM Link Policy maker is assumed shared between Tx as single 2-lane DisplayPort link to TM interface to single DisplayPort display device. the Host and TC358867XBG chip. - In auto correction = 0 mode, control link Video stream source is from MIPI DPI Host. training MODE S2P: TC358867XBG uses only Parallel TM - Initiate Display device capabilities read and output port and disables DisplayPort Tx to configure TC358867XBG accordingly. interface to single RGB display device. Video Video timing generation as per panel stream source is from MIPI DSI Host. requirement. Power supply inputs SSCG with to 30 kHz modulation to reduce Core and MIPI D-PHY: 1.2 V 0.06 V EMI. Digital I/O: 1.8 V 0.09 V TM Built in PRBS7 Generator to test DisplayPort TM DisplayPort : 1.8 V 0.09 V Link. TM DisplayPort : 1.2 V 0.06 V RGB Parallel Output Interface: Power Consumptions (Typical value based TM RGB888 output (DisplayPort disabled) with on estimations) only DSI input supported in this mode Power-down mode (DSI-Rx in ULPS, DP PHY PCLK max. = 100 MHz & PLLs disabled, clocks stopped): Polarity control for PCLK, VSYNC, HSYNC & - DSI Rx: 0.01 mW DE - DP PHY: 2.34 mW 2 I C Interface: - PLL9: 0.01 mW 2 I C slave interface for chip register set access - Core: 0.96 mW enabled using a boot-strap option. - Rest: 0.01 mW 2 Normal operation (1920 1080 resolution with I C compliant slave interface support for normal DSI-Rx in 4-lane 925 Mbps per lane, DP PHY (100 kHz) and fast mode (400 kHz). in dual lane link 2.7 Gbps per lane): GPIO Interface: - DSI Rx: 21.79 mW 2 bits of GPIO (shared with other digital logic). - DP PHY: 142.70 mW 2 Direction controllable by Host I C accesses. - PLL9: 2.42 mW - Core: 87.64 mW - IOs: 1.68 mW Package - 0.65mm ball pitch, 80 balls, 7 7 mm BGA package 2018 2 / 20 2018-05-28 Toshiba Electronic Devices & Storage Corporation Rev.1.1