TC74VHC138FT(EL,K) Toshiba

TC74VHC138F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC138F,TC74VHC138FT,TC74VHC138FK 3-to-8 Line Decoder The TC74VHC138 is an advanced high speed CMOS 3-to-8 TC74VHC138F DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y-0 Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade TC74VHC138FT connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features TC74VHC138FK High speed: t = 5.7 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V NIH NIL CC (min) Power down protection is provided on all inputs. Balanced propagation delays: t t pLH pHL Wide operating voltage range: V = 2 V to 5.5 V CC (opr) Pin and function compatible with 74ALS138 Weight SOP16-P-300-1.27A : 0.18 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) 1 2012-02-29 TC74VHC138F/FT/FK Pin Assignment A 1 16 VCC B 2 15 Y0 C 14 Y1 3 G 2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 (top view) IEC Logic Symbol BIN/OCT DMUX (1) (15) (1) (15) A 1 0 Y0 A 0 0 Y0 0 (2) (14) (2) (14) B 2 1 Y1 B G 1 Y1 7 (3) (13) (3) (13) C 4 2 Y2 C 2 2 Y2 (12) (12) 3 Y3 3 Y3 (11) (11) 4 Y4 4 Y4 & & (6) (10) (6) (10) G1 5 Y5 G1 5 Y5 (4) (9) (4) (9) G2A EN 6 Y6 G2A 6 Y6 (5) (7) (5) (7) G2B 7 Y7 G2B 7 Y7 Truth Table Inputs Outputs Selected Enable Select Output Y0 Y1 Y2 Y3 Y4 Y5 Y 6 Y 7 G1 G2A G2B C B A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y 0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y 3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y 5 H L L H H L H H H H H H L H Y 6 H L L H H H H H H H H H H L Y 7 X: Dont care 2 2012-02-29