TC74VHC165FT(EL,K) Toshiba

TC74VHC165F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC165F, TC74VHC165FT, TC74VHC165FK 8-Bit Shift Register (P-IN, S-OUT) TC74VHC165F The TC74VHC165 is an advanced high speed CMOS 8-BIT PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER 2 fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It consists of parallel-in or serial-in, serial-out 8-bit shift register with a gated clock input. When the SHIFT/ LOAD input is held high, the serial data input is enabled and the eight frip-frops perform serial shifting with each clock pulse. TC74VHC165FT When the SHIFT/ LOAD input is held low, the parallel data is loaded synchronously into the register at positive going transition of the clock pulse. The CK-INH input should be shifted high only when the CK input is held high. An Input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and on two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. TC74VHC165FK Features High speed: f = 150 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Power down protection is provided on all inputs. Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 V to 5.5 V CC Weight Pin and function compatible with 74ALS165 SOP16-P-300-1.27A: 0.18 g (typ.) TSSOP16-P-0044-0.65A: 0.06 g (typ.) VSSOP16-P-0030-0.50: 0.02 g (typ.) Start of commercial production 1992-05 1 2014-03-01 TC74VHC165F/FT/FK Pin Assignment IEC Logic Symbol SRG 8 S/L 1 16 V S/L (1) CC C1 LOAD (15) CK INH CK 2 15 CK INH > 1 C2/ (2) CK E 14 D 3 (10) SI 2D (11) F 4 13 C A 1D (12) B 1D G 5 12 B (13) C (14) D H 6 11 A (3) E (4) QH 7 10 SI F (5) G (9) GND 8 QH 9 QH (6) H 1D (7) QH Truth Table Internal Inputs Outputs Outputs SHIFT/ CK SERIAL PARALLEL CK QA QB QH QH LOAD INH IN AH L X X X ah a b h h H L H X H QA QG QG n n n H L L X L QA QG QG n n n H L H X H QA QG QG n n n H L L X L QA QG QG n n n H X H X X No Change H H X X X No Change X: Dont care ah: The level of steady state input voltage at inputs A through H respectively QA to QG : The level of QA to QG, respectively, before the most recent positive transition of the CK. n n 2 2014-03-01