IRFIB5N65A www.vishay.com Vishay Siliconix Power MOSFET FEATURES D TO-220 FULLPAK Low gate charge Q results in simple drive g requirement Improved gate, avalanche and dynamic dV/dt ruggedness G Fully characterized capacitance and avalanche voltage and current Material categorization: for definitions of compliance SS S DD please see www.vishay.com/doc 99912 G N-Channel MOSFET APPLICATIONS Switch mode power supply (SMPS) PRODUCT SUMMARY Uninterruptible power supply V (V) 650 DS High speed power switching R ()V = 10 V 0.93 DS(on) GS High voltage isolation = 2.5 kV (t = 60 s, f = 60 Hz) RMS Q (Max.) (nC) 48 g Q (nC) 12 gs TYPICAL SMPS TOPOLOGIES Q (nC) 19 gd Single transistor flyback Configuration Single Single transistor forward ORDERING INFORMATION Package TO-220 FULLPAK Lead (Pb)-free IRFIB5N65APbF ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted C PARAMETER SYMBOLLIMITUNIT Drain-source voltage V 650 DS V Gate-source voltage V 30 GS e Continuous drain current T = 25 C 5.1 C V at 10 V I GS D Continuous drain current T = 100 C 3.2 A C a Pulsed drain current I 21 DM Linear derating factor 0.48 W/C b Single pulse avalanche energy E 325 mJ AS a Repetitive avalanche current I 5.2 A AR a Repetitive avalanche energy E 6mJ AR Maximum power dissipation T = 25 C P 60 W C D c Peak diode recovery dV/dt dV/dt 2.8 V/ns Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) For 10 s 300 10 lbf in Mounting torque 6-32 or M3 screw 1.1 N m Notes a. Repetitive rating pulse width limited by maximum junction temperature (see fig. 11) b. Starting T = 25 C, L = 24 mH, R = 25 , I = 5.2 A (see fig. 12) J G AS c. I 5.2 A, dI/dt 90 A/s, V V , T 150 C SD DD DS J d. 1.6 mm from case e. Drain current limited by maximum junction temperature S21-0471-Rev. C, 17-May-2021 Document Number: 91174 1 For technical questions, contact: hvmos.techsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 IRFIB5N65A www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOLTYP. MAX. UNIT Maximum junction-to-ambient R -65 thJA C/W Maximum junction-to-case (drain) R -2.1 thJC SPECIFICATIONS T = 25 C, unless otherwise noted J PARAMETER SYMBOLTEST CONDITIONS MIN.TYP.MAX.UNIT Static Drain-ssource breakdown voltage V V = 0 V, I = 250 A 650 - - V DS GS D d V temperature coefficient V /T Reference to 25 C, I = 1 mA - 670 - mV/C DS DS J D Gate-source threshold voltage V V = V , I = 250 A 2.0 - 4.0 V GS(th) DS GS D Gate-source leakage I V = 30 V - - 100 nA GSS GS V = 650 V, V = 0 V - - 25 DS GS Zero gate voltage drain current I A DSS V = 520 V, V = 0 V, T = 125 C - - 250 DS GS J b Drain-source on-state resistance R V = 10 V I = 3.1 A - - 0.93 DS(on) GS D Forward transconductance g V = 50 V, I = 3.1 A 3.9 - - S fs DS D Dynamic Input capacitance C - 1417 - iss V = 0 V, GS Output capacitance C -V = 25 V, 177- oss DS f = 1.0 MHz, see fig. 5 Reverse transfer capacitance C -7.0- rss pF V = 1.0 V, f = 1.0 MHz - 1912 - DS Output capacitance C oss V = 0 V V = 520 V, f = 1.0 MHz - 48 - GS DS c Effective output capacitance C eff. V = 0 V to 520 V -84 - oss DS Total gate charge Q -- 48 g I = 5.2 A, V = 400 V D DS Gate-source charge Q --V = 10 V 12 nC gs GS b see fig. 6 and 13 Gate-drain charge Q --19 gd Turn-on delay time t -14 - d(on) V = 325 V, I = 5.2 A DD D Rise time t -20 - r R = 9.1 , R = 62 , ns G D b Turn-off delay time t -34- d(off) see fig. 10 Fall time t -18- f Drain-Source Body Diode Characteristics MOSFET symbol D -- 5.2 Continuous source-drain diode current I S showing the A integral reverse G a p - n junction diode Pulsed diode forward current I -- 21 SM S b Body diode voltage V T = 25 C, I = 5.2 A, V = 0 V -- 1.5 V SD J S GS Body diode reverse recovery time t - 493 739 ns rr b T = 25 C, I = 5.2 A, dI/dt = 100 A/s J F Body diode reverse recovery charge Q -2.1 3.2 C rr Forward turn-on time t Intrinsic turn-on time is negligible (turn-on is dominated by L and L ) on S D Notes a. Repetitive rating pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width 300 s duty cycle 2 % c. C eff. is a fixed capacitance that gives the same charging time as C while V is rising from 0 % to 80 % V oss oss DS DS d. t = 60 s, f = 60 Hz S21-0471-Rev. C, 17-May-2021 Document Number: 91174 2 For technical questions, contact: hvmos.techsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000