P GND V IN GH GL C GND VDRV SiC620R, SiC620AR www.vishay.com Vishay Siliconix 60 A VRPower Integrated Power Stage DESCRIPTION FEATURES Thermally enhanced PowerPAK MLP55-31L The SiC620R and SiC620AR are integrated power stage double cooling package solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density Vishays Gen IV MOSFET technology and a low performance. Packaged in Vishays proprietary 5 mm x 5 mm side MOSFET with integrated Schottky diode MLP package, SiC620R and SiC620AR enables voltage Delivers up to 60 A continuous current regulator designs to deliver up to 60 A continuous current 95 % peak efficiency per phase. High frequency operation up to 1.5 MHz The internal power MOSFETs utilizes Vishays Power MOSFETs optimized for 12 V input stage state-of-the-art Gen IV TrenchFET technology that delivers 3.3 V (SiC620AR) / 5 V (SiC620R) PWM logic with tri-state industry benchmark performance to significantly reduce and hold-off switching and conduction losses. Zero current detect control for light load efficiency The SiC620R and SiC620AR incorporates an advanced improvement MOSFET gate driver IC that features high current driving Low PWM propagation delay (< 20 ns) capability, adaptive dead-time control, an integrated bootstrap Schottky diode, a thermal warning (THWn) that Thermal monitor flag alerts the system of excessive junction temperature, and Under voltage lockout for V CIN zero current detect to improve light load efficiency. The Material categorization: for definitions of compliance drivers are also compatible with a wide range of PWM please see www.vishay.com/doc 99912 controllers and supports tri-state PWM, 3.3 V (SiC620AR) / 5 V (SiC620R) PWM logic. APPLICATIONS Multi-phase VRDs for CPU, GPU, and memory TYPICAL APPLICATION DIAGRAM 5V V IN BOOT PHASE V CIN ZCD EN V SWH DSBL V OUT Gate PWM driver PWM controller THWn Fig. 1 - SiC620R and SiC620AR Typical Application Diagram S18-1233, Rev. B 17-Dec-2018 Document Number: 63589 1 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiC620R, SiC620AR www.vishay.com Vishay Siliconix PINOUT CONFIGURATION 33 GL 31 30 29 28 27 26 25 24 24 25 26 27 28 29 30 31 PWM 23 V V 23 1 PWM 1 SWH SWH SMOD 2 22 V V 22 2 SMOD 32 SWH SWH AGND V 3 21 V V 21 3 V SWH SWH CIN CIN A 4 20 V V 20 4 A GND SWH SWH GND BOOT 5 19 V V 19 5 BOOT SWH SWH GH 6 18 V V 18 6 GH SWH SWH PHASE PHASE 7 17 V V 17 7 SWH SWH V 8 16 V IN V V 16 8 SWH IN SWH 10 11 12 13 14 15 9 15 14 13 12 11 10 9 Top view Bottom view Fig. 2 - SiC620R and SiC620AR Pin Configuration PIN CONFIGURATION PIN NUMBER NAME FUNCTION 1PWM PWM control input 2 ZCD EN ZCD control. Active low 3V Supply voltage for internal logic circuitry CIN 4, 32 C Analog ground for the driver IC GND 5 BOOT High side driver bootstrap voltage 6GH High side gate signal 7 PHASE Return path of high side gate driver 8 to 11, 34 V Power stage input voltage. Drain of high side MOSFET IN 12 to 15, 28, 35 P Power ground GND 16 to 26 V Switch node of the power stage SWH 27, 33 GL Low side gate signal 29 V Supply voltage for internal gate driver DRV 30 THWn Thermal warning open drain output 31 DSBL Disable pin. Active low S18-1233, Rev. B 17-Dec-2018 Document Number: 63589 2 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 V DSBL IN V THDn IN V V DRV IN P GND P GL GND P V SWH GND P V SWH GND V P GND SWH P V GND SWH P V GND SWH P V GND SWH P GL GND P GND V V IN DRV V THDn IN V DSBL IN