SiZF918DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET With Schottky Diode FEATURES TrenchFET Gen IV power MOSFET SkyFET low side MOSFET with integrated Schottky 100 % R and UIS tested g Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 V /D APPLICATIONS N-Channel 1 IN 1 MOSFET CPU core power Computer / server peripherals G /G HS 1 PRODUCT SUMMARY POL G Return/S V /S -D 1 1 SW 1 2 CHANNEL-1 CHANNEL-2 Synchronous buck converter V (V) 30 30 DS Telecom DC/DC R max. () at V = 10 V 0.0040 0.0019 DS(on) GS Schottky R max. () at V = 4.5 V 0.0067 0.0027 G /G DS(on) GS LS 2 Diode Q typ. (nC) 7 17.3 g a I (A) 40 60 D N-Channel 2 MOSFET Configuration Dual GND/S 2 ORDERING INFORMATION Package PowerPAIR 6 x 5F Lead (Pb)-free and halogen-free SiZF918DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +16, -12 GS a a T = 25 C 40 60 C a a T = 70 C 40 60 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 23 35 A b, c b, c T = 70 C 18.4 28 A A Pulsed drain current (t = 100 s) I 130 100 DM a T = 25 C 22 60 C Continuous source-drain diode current I S b, c b, c T = 25 C 2.8 6.1 A Single pulse avalanche current I 15 18 AS L = 0.1 mH Single pulse avalanche energy E 11.3 16 mJ AS T = 25 C 26.6 50 C T = 70 C 17 32 C Maximum power dissipation P W D b, c b, c T = 25 C 3.4 3.7 A b, c b, c T = 70 C 2.2 2.4 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 30 37 27 34 thJA C/W Maximum junction-to-case (source) Steady state R 3.8 4.722.5 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR 6 x 5F is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 77 C/W for channel-1 and 70 C/W for channel-2 S20-0024-Rev. B, 03-Feb-2020 Document Number: 75963 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiZF918DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 30 - - Drain-source breakdown voltage V V = 0 V, I = 250 A DS GS D Ch-2 30 - - Ch-1 36 - - Drain-source breakdown voltage V V = 0 V, t = 1 s V DSt GS (transient) c (transient) Ch-2 36 - - Ch-1 1.1 - 2.4 Gate-source threshold voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.0 - 2.3 V = 0 V, V = +20 V, -16 V Ch-1 - - 100 DS GS Gate-source leakage I nA GSS V = 0 V, V = +16 V, -12 V Ch-2 - - 100 DS GS Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - 20 350 Zero Gate voltage drain current I A DSS Ch-1 - - 5 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - 200 3000 Ch-1 20 - - b On-state drain current I V 5 V, V = 10 V A D(on) DS GS Ch-2 20 - - V = 10 V, I = 10 A Ch-1 - 0.0029 0.0040 GS D V = 10 V, I = 10 A Ch-2 - 0.0012 0.0019 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.0047 0.0068 GS D V = 4.5 V, I = 5 A Ch-2 - 0.0018 0.0027 GS D V = 10 V, I = 20 A Ch-1 - 53 - DS D b Forward transconductance g S fs V = 10 V, I = 20 A Ch-2 87 - DS D a Dynamic Ch-1 - 1060 - Input capacitance C iss Ch-2 - 2650 - Channel-1 Ch-1 - 600 - V = 15 V, V = 0 V, f = 1 MHz Output capacitance C pF DS GS oss Ch-2 - 1240 - Ch-1 - 45 - Reverse transfer capacitance C rss Channel-2 Ch-2 - 140 - V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.042 0.085 C /C ratio rss iss Ch-2 0.053 0.106 V = 15 V, V = 10 V, I = 10 A Ch-1 - 14.6 22 DS GS D V = 15 V, V = 10 V, I = 10 A Ch-2 - 37 56 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 10 A Ch-1 7 11 DS GS D V = 15 V, V = 4.5 V, I = 10 A Ch-2 - 17.4 27 DS GS D Ch-1 - 3 - Channel-1 Gate-source charge Q nC gs Ch-2 - 6.1 - V = 15 V, V = 4.5 V, I = 10 A DS GS D Channel-2 Ch-1 - 1.5 - Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-2 - 3.5 - Ch-1 - 14 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 31 - Ch-1 0.2 1 2 Gate resistance R f = 1 MHz g Ch-2 0.1 0.5 1 Ch-1 - 17 35 Turn-on delay time t d(on) Channel-1 Ch-2 - 22 45 V = 15 V, R = 3 DD L Ch-1 - 45 90 I 5 A, V = 4.5 V, R = 1 Rise time t D GEN g r Ch-2 - 55 110 ns Ch-1 - 20 40 Turn-off delay time t d(off) Channel-2 Ch-2 - 30 60 V = 15 V, R = 3 DD L Ch-1 - 10 20 I 5 A, V = 4.5 V, R = 1 D GEN g Fall time t f Ch-2 - 10 20 S20-0024-Rev. B, 03-Feb-2020 Document Number: 75963 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000