SiZF920DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET with Schottky Diode FEATURES TrenchFET Gen IV power MOSFET SkyFET low-side MOSFET with integrated Schottky 100 % R and UIS tested g Material categorization: for definitions of compliance please see www.vishay.com/doc 99912 V /D APPLICATIONS N-Channel 1 IN 1 MOSFET CPU core power PRODUCT SUMMARY G /G HS 1 Computer / server peripherals CHANNEL-1 CHANNEL-2 G Return/S V /S -D POL 1 1 SW 1 2 V (V) 30 30 DS Synchronous buck converter R max. ( ) at V = 10 V 0.00307 0.00105 DS(on) GS Telecom DC/DC R max. ( ) at V = 4.5 V 0.00530 0.00145 DS(on) GS Schottky G /G LS 2 Diode Q typ. (nC) 9 38.6 g a I (A) 76 197 D N-Channel 2 MOSFET Configuration Dual GND/S 2 ORDERING INFORMATION Package PowerPAIR 6 x 5F Lead (Pb)-free and halogen-free SiZF920DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1CHANNEL-2UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +16, -12 GS T = 25 C 76 197 C T = 70 C 61 158 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 28 49 A b, c b, c T = 70 C 23 39 A A Pulsed drain current (t = 100 s) I 130 130 DM T = 25 C 26 122 C Continuous source-drain diode current I S b, c b, c T = 25 C 3.6 7.4 A Single pulse avalanche current I 16 28 AS L = 0.1 mH Single pulse avalanche energy E 13 39 mJ AS T = 25 C 28 74 C T = 70 C 18 47 C Maximum power dissipation P W D b, c b, c T = 25 C 3.9 4.5 A b, c b, c T = 70 C 2.5 2.9 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 25 32 22 28 thJA C/W Maximum junction-to-case (source) Steady state R 3.5 4.4 1.3 1.7 thJC Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 65 C/W for channel-1 and 65 C/W for channel-2 S18-1125 Rev. A, 12-Nov-2018 Document Number: 79595 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiZF920DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Ch-1 30 - - Drain-source breakdown voltage V V = 0 V, I = 250 A DS GS D Ch-2 30 - - V Ch-1 1.1 - 2.4 Gate-source threshold voltage V V = V , I = 250 A GS(th) DS GS D Ch-2 1.1 - 2.2 V = 0 V, V = +20 V, -16 V Ch-1 - - 100 DS GS Gate-source leakage I nA GSS V = 0 V, V = +16 V, -12 V Ch-2 - - 100 DS GS Ch-1 - - 1 V = 30 V, V = 0 V DS GS Ch-2 - 60 400 Zero Gate voltage drain current I A DSS Ch-1 - - 5 V = 30 V, V = 0 V, T = 55 C DS GS J Ch-2 - 350 4000 Ch-1 20 - - b On-state drain current I V 5 V, V = 10 V A D(on) DS GS Ch-2 20 - - V = 10 V, I = 10 A Ch-1 - 0.00230 0.00307 GS D V = 10 V, I = 10 A Ch-2 - 0.00070 0.00105 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.00380 0.00530 GS D V = 4.5 V, I = 5 A Ch-2 - 0.00095 0.00145 GS D V = 15 V, I = 25 A Ch-1 - 65 - DS D b Forward transconductance g S fs V = 15 V, I = 25 A Ch-2 135 - DS D a Dynamic Ch-1 - 1300 - Input capacitance C iss Ch-2 - 5230 - Channel-1 Ch-1 - 700 - V = 15 V, V = 0 V, f = 1 MHz DS GS Output capacitance C pF oss Ch-2 - 2920 - Ch-1 - 35 - Reverse transfer capacitance C rss Channel-2 Ch-2 - 360 - V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 - 0.027 0.054 C /C ratio rss iss Ch-2 0.069 0.140 V = 15 V, V = 10 V, I = 10 A Ch-1 - 19 29 DS GS D V = 15 V, V = 10 V, I = 10 A Ch-2 - 83 125 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 10 A Ch-1 9 14 DS GS D V = 15 V, V = 4.5 V, I = 10 A Ch-2 - 38.6 58 DS GS D Channel-1 Ch-1 - 4.4 - nC Gate-source charge Q gs V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-2 - 17 - Ch-1 - 2 - Channel-2 Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 10 A Ch-2 - 9.2 - DS GS D Ch-1 - 17 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 46 - Ch-1 0.2 1 2 Gate resistance R f = 1 MHz g Ch-2 0.1 0.4 0.8 S18-1125 Rev. A, 12-Nov-2018 Document Number: 79595 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000