3.3 mm SiZ200DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3S G 2 TrenchFET Gen IV power MOSFETs S 2 S 2 8 S 7 2 6 100 % R and UIS tested g 5 Optimized Q /Q ratio improves switching gs gs D 1 characteristics Material categorization: 1 2 3 G for definitions of compliance please se e 1 D 1 4 1 D 1 D www.vishay.com/doc 99912 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 30 30 DS N-Channel 1 S /D R max. ( ) at V = 10 V 0.0055 0.0058 1 2 DS(on) GS POL MOSFET R max. ( ) at V = 4.5 V 0.0073 0.0077 DS(on) GS Synchronous buck converter Q typ. (nC) 8.4 9.2 g G 2 Telecom DC/DC a a I (A) 61 60 N-Channel 2 D MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3S Lead (Pb)-free and halogen-free SiZ200DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V +20, -16 +20, -16 GS a a T = 25 C 61 60 C T = 70 C 49 48 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 22 22 A b, c b, c T = 70 C 18 17 A A Pulsed drain current (100 s pulse width) I 130 130 DM T = 25 C 27 27 C Continuous source drain diode current I S b, c b, c T = 25 C 3.6 3.6 A Single pulse avalanche current I 15 15 AS L = 0.1 mH Single pulse avalanche energy E 11 11 mJ AS T = 25 C 33 33 C T = 70 C 21 21 C Maximum power dissipation P W D b, c b, c T = 25 C 4.3 4.3 A b, c b, c T = 70 C 2.8 2.8 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 23 29 23 29 thJA C/W Maximum junction-to-case (drain) Steady state R 3 3.833.8 thJC Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR 3 x 3S is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 64 C/W for channel-1 and 64 C/W for channel-2 S19-0937-Rev. B, 11-Nov-2019 Document Number: 75033 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3.3 mm S /D 1 2 (Pin 9) SiZ200DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 30 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 30 - - GS D I = 250 A Ch-1 - 13 - D V Temperature coefficient V /T DS DS J I = 250 A Ch-2 - 18 - D mV/C I = 250 A Ch-1 - -5.2 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - -5.1 - D V = V , I = 250 A Ch-1 1.1 - 2.4 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.4 DS GS D V = 0 V, V = +20 V, -16 V Ch-1 - - 100 DS GS Gate source leakage I nA GSS V = 0 V, V = +20 V, -16 V Ch-2 - - 100 DS GS V = 30 V, V = 0 V Ch-1 - - 1 DS GS V = 30 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 - - 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 - - 5 DS GS J V 5 V, V = 10 V Ch-1 10 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 10 - - DS GS V = 10 V, I = 10 A Ch-1 - 0.0045 0.0055 GS D V = 10 V, I = 10 A Ch-2 - 0.0048 0.0058 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 7 A Ch-1 - 0.0057 0.0073 GS D V = 4.5 V, I = 7 A Ch-2 - 0.0060 0.0077 GS D V = 10 V, I = 30 A Ch-1 - 118 - DS D b Forward transconductance g S fs V = 10 V, I = 30 A Ch-2 - 105 - DS D a Dynamic Ch-1 - 1510 - Input capacitance C iss Ch-2 - 1600 - Channel-1 Ch-1 - 590 - Output capacitance C pF oss V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 620 - Ch-1 - 28 - Channel-2 Reverse transfer capacitance C rss V = 15 V, V = 0 V, f = 1 MHz Ch-2 - 27 - DS GS Ch-1 - 0.019 0.040 C /C ratio rss iss Ch-2 - 0.017 0.035 V = 15 V, V = 10 V, I = 10 A Ch-1 - 18.3 28 DS GS D V = 15 V, V = 10 V, I = 10 A Ch-2 - 20 30 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 10 A Ch-1 - 8.4 13 DS GS D V = 15 V, V = 4.5 V, I = 10 A Ch-2 - 9.2 14 DS GS D Ch-1 - 3.7 - Channel-1 Gate-source charge Q nC gs V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-2 - 4.5 - Ch-1 - 1 - Channel-2 Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 10 A DS GS D Ch-2 - 1 - Ch-1 - 17 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 18 - Ch-1 0.28 1.4 2.8 Gate resistance R f = 1 MHz g Ch-2 0.2 1 2 S19-0937-Rev. B, 11-Nov-2019 Document Number: 75033 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000