3 m3 mmm SiZ346DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PowerPAIR 3 x 3 G 2 S TrenchFET Gen IV power MOSFETs 2 8 S 2 7 S 2 6 100 % R and UIS tested g 5 S /D 1 2 Optimized Q /Q ratio improves switching (Pin 9) gs gs D characteristics 1 1 Material categorization: 2 G 1 3 D for definitions of compliance please see 1 11 4 D 1 www.vishay.com/doc 99912 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 30 30 DS N-Channel 1 S /D R max. ( ) at V = 10 V 0.0285 0.0115 1 2 DS(on) GS POL MOSFET R max. ( ) at V = 4.5 V 0.0370 0.0153 DS(on) GS Synchronous buck converter Q typ. (nC) 3.2 4.5 g G 2 Telecom DC/DC g a I (A) 17 30 N-Channel 2 D MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 3 x 3 Lead (Pb)-free and halogen-free SiZ346DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 30 30 DS V Gate-source voltage V 20 +20, -16 GS T = 25 C 17 30 C T = 70 C 13.8 24 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 8 14.1 A b, c b, c T = 70 C 6.3 11.3 A A Pulsed drain current (100 s pulse width) I 25 100 DM T = 25 C 13.4 13.9 C Continuous source drain diode current I S b, c b, c T = 25 C 2.8 3.1 A Single pulse avalanche current I 910 AS L = 100 mH Single pulse avalanche energy E 4.1 5 mJ AS T = 25 C 16 16.7 C T = 70 C 10.3 10.7 C Maximum power dissipation P W D b, c b, c T = 25 C 3.4 3.7 A b, c b, c T = 70 C 2.2 2.4 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 30 37 27 34 thJA C/W Maximum junction-to-case (drain) Steady state R 6.3 7.867.5 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 71 C/W for channel-1 and 69 C/W for channel-2 g. T = 25 C C S17-0249-Rev. A, 20-Feb-17 Document Number: 68128 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3 mm3 mmSiZ346DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 30 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 30 - - GS D I = 250 A Ch-1 - 31 - D V Temperature coefficient V /T DS DS J I = 250 A Ch-2 - 20 - D mV/C I = 250 A Ch-1 - -4.9 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - -5.6 - D V = V , I = 250 A Ch-1 1.1 - 2.2 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.2 - 2.4 DS GS D V = 0 V, V = +20 V, -20 V Ch-1 - - 100 DS GS Gate source leakage I nA GSS V = 0 V, V = +20 V, -16 V Ch-2 - - 100 DS GS V = 30 V, V = 0 V Ch-1 - - 1 DS GS V = 30 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 - - 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 - - 5 DS GS J V 5 V, V = 10 V Ch-1 10 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 10 - - DS GS V = 10 V, I = 10 A Ch-1 - 0.0230 0.0285 GS D V = 10 V, I = 14.4 A Ch-2 - 0.0084 0.0115 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 5 A Ch-1 - 0.0300 0.0370 GS D V = 4.5 V, I = 13 A Ch-2 - 0.0111 0.0153 GS D V = 10 V, I = 10 A Ch-1 - 17 - GS D b Forward transconductance g S fs V = 10 V, I = 14.4 A Ch-2 - 17 - GS D a Dynamic Ch-1 - 325 - Input capacitance C iss Ch-2 - 650 - Ch-1 - 66 - Channel-1 Output capacitance C pF oss V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-2 - 236 - Ch-1 - 33 - Channel-2 Reverse transfer capacitance C rss V = 15 V, V = 0 V, f = 1 MHz Ch-2 - 20 - DS GS Ch-1 - 0.1 0.2 C /C ratio rss iss Ch-2 - 0.03 0.06 V = 15 V, V = 10 V, I = 5 A Ch-1 - 6.6 10 DS GS D V = 15 V, V = 10 V, I = 14.4 A Ch-2 - 10 20 DS GS D Total gate charge Q g V = 15 V, V = 4.5 V, I = 5 A Ch-1 - 3.2 5 DS GS D V = 15 V, V = 4.5 V, I = 14.4 A Ch-2 - 4.5 9 DS GS D Ch-1 - 1 - Channel-1 Gate-source charge Q nC gs V = 15 V, V = 4.5 V, I = 5 A DS GS D Ch-2 - 2.1 - Ch-1 - 1.2 - Channel-2 Gate-drain charge Q gd V = 15 V, V = 4.5 V, I = 14.4 A DS GS D Ch-2 - 0.7 - Ch-1 - 1.5 - Output charge Q V = 15 V, V = 0 V oss DS GS Ch-2 - 6.6 - Ch-1 0.2 0.85 1.7 Gate resistance R f = 1 MHz g Ch-2 0.3 1.4 2.8 S17-0249-Rev. A, 20-Feb-17 Document Number: 68128 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000