SPICE Device Model SQJ463EP www.vishay.com Vishay Siliconix P-Channel 40 V (D-S) MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical P-Channel Vertical DMOS characteristics of the p-channel vertical DMOS. The Macro Model (Subcircuit Model) subcircuit model is extracted and optimized over the - 55 C Level 3 MOS to + 125 C temperature ranges under the pulsed 0 V to 10 V Apply for both Linear and Switching Application gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain Accurate over the - 55 C to + 125 C Temperature Range feedback capacitance network is used to model the gate Model the Gate Charge, Transient, and Diode Reverse charge characteristics while avoiding convergence Recovery Characteristics difficulties of the switched C model. All model parameter gd values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC D C GD R M 1 2 3 DBD Gy Gx + G R G M ETCV C 1 GS S Note This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. S12-2558-Rev. B, 29-Oct-12 Document Number: 66760 1 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000SPICE Device Model SQJ463EP www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J SIMULATED MEASURED PARAMETER SYMBOLTEST CONDITIONS DATA DATA UNIT Static Gate-Source Threshold Voltage V V = V , I = - 250 A 1.4 - V GS(th) DS GS D V = - 10 V, I = - 18 A 0.008 0.007 GS D a Drain-Source On-State Resistance R DS(on) V = - 4.5 V, I = - 15 A 0.013 0.011 GS D a Forward Transconductance g V = - 15 V, I = - 18 A 42 45 S fs DS D Diode Forward Voltage V I = - 4.5 A - 0.70 - 0.80 V SD S b Dynamic Input Capacitance C 4760 4700 iss Output Capacitance C 700V = - 20 V, V = 0 V, f = 1 MHz625 pF oss DS GS Reverse Transfer Capacitance C 400460 rss Total Gate Charge Q 95 97 g Gate-Source Charge Q 14V = - 20 V, V = - 10 V, I = - 18.6 A14 nC gs DS GS D Gate-Drain Charge Q 2323 gd Notes a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. S12-2558-Rev. B, 29-Oct-12 Document Number: 66760 2 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000