W25M02GV Featuring 3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS Publication Release Date: May 09, 2018 Revision F W25M02GV Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7 3.2 Pad Description WSON 8x6-mm .......................................................................................... 7 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 8 3.4 Pin Description SOIC 300-mil ............................................................................................... 8 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9 3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 9 4. PIN DESCRIPTIONS ...................................................................................................................... 10 4.1 Serial MCP (SpiStack ) Device Configuration ................................................................... 10 4.2 Chip Select (/CS) ................................................................................................................ 10 4.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10 4.4 Write Protect (/WP) ............................................................................................................. 11 4.5 HOLD (/HOLD) ................................................................................................................... 11 4.6 Serial Clock (CLK) .............................................................................................................. 11 5. SINGLE DIE (W25N01GV) BLOCK DIAGRAM .............................................................................. 12 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 13 6.1 Device Operation Flow ....................................................................................................... 13 6.1.1 Stacked Die Operations ........................................................................................................ 13 6.1.2 Standard SPI Instructions ..................................................................................................... 13 6.1.3 Dual SPI Instructions ............................................................................................................ 14 6.1.4 Quad SPI Instructions ........................................................................................................... 14 6.1.5 Hold Function ........................................................................................................................ 14 6.2 Write Protection .................................................................................................................. 15 7. PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 16 7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 16 7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) Volatile Writable, OTP lockable .................. 16 7.1.2 Write Protection Enable Bit (WP-E) Volatile Writable, OTP lockable ................................. 17 7.1.3 Status Register Protect Bits (SRP1, SRP0) Volatile Writable, OTP lockable ..................... 17 7.2 Configuration Register / Status Register-2 (Volatile Writable) ........................................... 18 7.2.1 One Time Program Lock Bit (OTP-L) OTP lockable .......................................................... 18 7.2.2 Enter OTP Access Mode Bit (OTP-E) Volatile Writable ..................................................... 18 7.2.3 Status Register-1 Lock Bit (SR1-L) OTP lockable ............................................................. 18 7.2.4 ECC Enable Bit (ECC-E) Volatile Writable ......................................................................... 19 7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) Volatile Writable ..................................... 19 7.3 Status Register-3 (Status Only) .......................................................................................... 20 7.3.1 Look-Up Table Full (LUT-F) Status Only............................................................................ 20 - 1 -