W25Q80BL 2.5V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: April 07,2014 - 1 - Revision G1 W25Q80BL Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES ............................................................................................................................ 6 3.1 Pin Configuration SOIC 150 / 208-mil, VSOP 150-mil .......................................................... 6 3.2 PAD Configuration WSON 6x5-mm, USON 2X3-MM .......................................................... 6 3.3 Pin Description SOIC, VSOP, WSON, USON ...................................................................... 7 3.4 Pin Descriptions .................................................................................................................... 8 3.4.1 Chip Select (/CS) ................................................................................................................... 8 3.4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ....................................... 8 3.4.3 Write Protect (/WP) ................................................................................................................ 8 3.4.4 HOLD (/HOLD) ....................................................................................................................... 8 3.5 Serial Clock (CLK) ................................................................................................................ 8 4. BLOCK DIAGRAM ............................................................................................................................ 9 5. FUNCTIONAL DESCRIPTION ....................................................................................................... 10 5.1 SPI OPERATIONS ............................................................................................................. 10 5.1.1 Standard SPI Instructions .................................................................................................... 10 5.1.2 Dual SPI Instructions ............................................................................................................ 10 5.1.3 Quad SPI Instructions .......................................................................................................... 10 5.1.4 Hold Function ....................................................................................................................... 10 5.2 WRITE PROTECTION ....................................................................................................... 11 5.2.1 Write Protect Features ......................................................................................................... 11 6. CONTROL AND STATUS REGISTERS ......................................................................................... 12 6.1 STATUS REGISTER .......................................................................................................... 12 6.1.1 BUSY.................................................................................................................................... 12 6.1.2 Write Enable Latch (WEL) ................................................................................................... 12 6.1.3 Block Protect Bits (BP2, BP1, BP0) ..................................................................................... 12 6.1.4 Top/Bottom Block Protect (TB) ............................................................................................. 12 6.1.5 Sector/Block Protect (SEC) .................................................................................................. 12 6.1.6 Complement Protect (CMP) ................................................................................................. 13 6.1.7 Status Register Protect (SRP1, SRP0) ................................................................................ 13 6.1.8 Erase/Program Suspend Status (SUS) ................................................................................ 13 6.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 13 6.1.10 Quad Enable (QE) .............................................................................................................. 14 6.1.11 Status Register Memory Protection (CMP = 0) .................................................................. 15 6.1.12 Status Register Memory Protection (CMP = 1) .................................................................. 16 6.2 INSTRUCTIONS ................................................................................................................. 17 6.2.1 Manufacturer and Device Identification ................................................................................ 17 (1) 6.2.2 Instruction Set Table 1 (Erase, Program Instructions) ...................................................... 18 - 2 -