DS1225AD-150+ Analog Devices

19-5625 Rev 11/10 DS1225AB/AD 64k Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the 1 28 VCC NC absence of external power A12 27 WE 2 Data is automatically protected during power A7 3 26 NC loss 4 25 A8 A6 A5 A9 5 24 Directly replaces 8k x 8 volatile static RAM 6 23 A11 A4 or EEPROM OE A3 7 22 Unlimited write cycles A2 8 21 A10 Low-power CMOS A1 9 20 CE A0 10 19 DQ7 JEDEC standard 28-pin DIP package DQ0 DQ6 11 18 Read and write access times of 70 ns 12 17 DQ1 DQ5 Lithium energy source is electrically 13 16 DQ2 DQ4 disconnected to retain freshness until power GND 14 15 DQ3 is applied for the first time 28-Pin ENCAPSULATED PACKAGE Full 10% V operating range (DS1225AD) CC 720-mil EXTENDED Optional 5% V operating range CC (DS1225AB) PIN DESCRIPTION Optional industrial temperature range of A0-A12 - Address Inputs -40C to +85C, designated IND DQ0-DQ7 - Data In/Data Out - Chip Enable CE WE - Write Enable OE - Output Enable V - Power (+5V) CC GND - Ground NC - No Connect DESCRIPTION The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the lithium CC energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 10 DS1225AB/AD READ MODE The DS1225AB and DS1225AD execute a read cycle whenever (Write Enable) is inactive (high) and WE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 13 CE OE address inputs (A -A ) defines which of the 8192 bytes of data is to be accessed. Valid data will be 0 12 available to the eight data output drivers within t (Access Time) after the last address input signal is ACC stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t for CE or t for OE rather than address access. CO OE WRITE MODE The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) before another cycle can be initiated. The OE control signal should be kept inactive WR (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in t from its falling edge. ODW DATA RETENTION MODE The DS1225AB provides full functional capability for V greater than 4.75 volts and write protects by CC 4.5 volts. The DS1225AD provides full-functional capability for V greater than 4.5 volts and write CC protects by 4.25 volts. Data is maintained in the absence of V without any additional support circuitry. CC The nonvolatile static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs CC automatically write protect themselves, all inputs become dont care, and all outputs become high- impedance. As V falls below approximately 3.0 volts, the power switching circuit connects the lithium CC energy source to RAM to retain data. During power-up, when V rises above approximately 3.0 volts, CC the power switching circuit connects external V to RAM and disconnects the lithium energy source. CC Normal RAM operation can resume after V exceeds 4.75 volts for the DS1225AB and 4.5 volts for the CC DS1225AD. FRESHNESS SEAL Each DS1225 is shipped from Maxim with the lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level of greater than V , the lithium energy source is CC TP enabled for battery backup operation. 2 of 9