19-5617 Rev 11/10 DS1265W 3.3V 8Mb Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 36 V CC absence of external power NC 2 35 A19 A18 3 34 NC Data is automatically protected during power 4 33 A15 A16 loss A14 5 32 A17 Unlimited write cycles A12 6 31 WE A7 7 30 A13 Low-power CMOS operation A6 8 29 A8 Read and write access times of 100ns A5 A9 9 28 Lithium energy source is electrically A4 10 27 A11 26 OE disconnected to retain freshness until power is A3 11 12 25 A2 A10 applied for the first time 13 24 CE A1 Optional industrial (IND) temperature range 14 23 A0 DQ7 of -40C to +85C DQ0 15 22 DQ6 16 21 DQ1 DQ5 17 20 DQ4 DQ2 18 19 GND DQ3 36-Pin Encapsulated Package 740mil Extended PIN DESCRIPTION A0A19 - Address Inputs DQ0DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+3.3V) CC GND - Ground NC - No Connect DESCRIPTION The DS1265W 8Mb nonvolatile (NV) SRAMs are 8,388,608-bit, fully static, NV SRAMs organized as 1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors V for an out-of-tolerance condition. When such a condition occurs, CC the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 DS1265W READ MODE The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 20 address inputs OE (A A ) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the 0 19 eight data output drivers within t (Access Time) after the last address input signal is stable, providing ACC that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t for CE or t for OE rather than t . CO OE ACC WRITE MODE The DS1265 devices execute a write cycle whenever WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) WR before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in t from its falling edge. ODW DATA-RETENTION MODE The DS1265W provides full functional capability for V greater than 3.0V and write protects by 2.8V. CC Data is maintained in the absence of V without any additional support circuitry. The nonvolatile static CC RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically write CC protect themselves, all inputs become dont care, and all outputs become high-impedance. As V falls CC below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V rises above approximately 2.5V, the power-switching circuit CC connects external V to RAM and disconnects the lithium energy source. Normal RAM operation can CC resume after V exceeds 3.0V. CC FRESHNESS SEAL Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level greater than V , the lithium CC TP energy source is enabled for battery backup operation. 2 of 8