APS12808L-3OBMX-BA AP Memory

APS12808L-3OBMx DDR OPI Xccela PSRAM Double-Data-Rate OPI Xccela PSRAM Specifications Features Single Supply Voltage Low Power Features o VDD = 2.7 to 3.6V o Partial Array Self-Refresh (PASR) o VDDQ = 2.7 to 3.6V o Auto Temperature Compensated Self- Refresh (ATCSR) by built-in temperature Interface: Octal SPI with DDR Xccela mode, two bytes transfers per one clock cycle sensor o User configurable refresh rate Performance: Clock rate up to 133MHz , Software Reset 266MB/s read/write throughput Reset Pin Available Organization: 128Mb, 16M x 8bits with 1024 Output Driver LVCMOS with programmable bytes page size drive strength o Column address: AY0 to AY9 Data Mask (DM) for write data o Row address: AX0 to AX13 Data Strobe (DQS) enabled highspeed read Refresh: Self-managed operation Operating Temperature Range Register Configurable write and read initial o Tc = -40C to +85C(standard range) latencies o Tc= -40C to +105C (extended range) Write Burst Length, maximum 1024 Byte, Maximum Standby Current minimum 2 Byte. o 700A 105C (extended range) Wrap & Hybrid Burst in 16/32/64/1K lengths. o 500A 85C Linear Burst Command o 280A 25C Row Boundary Crossing (RBX) o read operations can be enabled via Mode Register o RBX Write is NOT supported o RA 13 Boundary Crossing is NOT supported between 2 dies APM Octal PSRAM Datasheet.pdf - Rev. 1.1b Dec 14, 2019 1 of 26 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved APS12808L-3OBMx DDR OPI Xccela PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Package Information ........................................................................................................ 3 3 Package Outline Drawing ................................................................................................. 4 4 Ordering Information ....................................................................................................... 5 5 Signal Table ...................................................................................................................... 6 6 Power-Up Initialization .................................................................................................... 7 6.1 Power-Up Initialization Method 1 (via. RESET pin) ............................................... 7 6.2 Power-Up Initialization Method 2 (via. Global Reset) ............................................ 8 7 Interface Description ....................................................................................................... 9 7.1 Address Space ......................................................................................................... 9 7.2 Burst Type & Length ................................................................................................ 9 7.3 Command/Address Latching ................................................................................... 9 7.4 Command Truth Table ............................................................................................ 9 7.5 Read Operation ..................................................................................................... 10 7.6 Write Operation .................................................................................................... 13 7.7 Control Registers ................................................................................................... 14 8 Electrical Specifications: ................................................................................................ 20 8.1 Absolute Maximum Ratings .................................................................................. 20 8.2 Pin Capacitance ..................................................................................................... 20 8.3 Decoupling Capacitor Requirement ...................................................................... 21 8.4 Operating Conditions ............................................................................................ 21 8.5 DC Characteristics ................................................................................................. 22 8.6 ISB Partial Array Refresh Current .......................................................................... 23 8.7 AC Characteristics ................................................................................................. 24 9 Change Log ..................................................................................................................... 26 APM Octal PSRAM Datasheet.pdf - Rev. 1.1b Dec 14, 2019 2 of 26 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved