APS1604M-SQRX-SN AP Memory

APS1604M-SQR QSPI PSRAM SPI/QPI PSRAM Specifications Features Single Supply Voltage Output Driver LVCMOS with programmable drive o V =1.62 to 1.98V DD strengths of 50, 100 and 200 Interface: SPI/QPI with SDR mode Dedicated Wrapped Burst read and write Performance: Clock rate up to commands o 144MHz for Wrapped Burst operation Linear 512 Length Burst is supported up to o 84MHz for Linear 512 Burst operation 84MHz and can cross page boundary as long as Organization: 16Mb, 2M x 8bits tCEM is met Addressable Bit Range: A 20:0 Register Configurable Wrap Lengths of 16, 32, 64 Page Size: 512 bytes and 512 Refresh: Self-managed Toggle Command to switch between Operating Temperature Range configurable wrap length and 32 bytes wrap o Tc= -40C to +85C (standard range) Software Reset o Tc= -40C to +105C (extended range) Maximum Standby Current o 150A 105C o 100A 85C o 25A 25C APM QSPI PSRAM Datasheet.pdf - Rev. 2.5 Nov 21, 2019 1 of 31 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved APS1604M-SQR QSPI PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Introduction ..................................................................................................................... 4 3 Package Information ........................................................................................................ 4 3.1 Package Types : SOP / USON (SN, ZR) , not to scale, Top view .............................. 4 4 Package Outline Drawing ................................................................................................. 5 4.1 SOP-8L(150), package code SN ............................................................................... 5 4.2 USON-8L 3x2mm, package code ZR ........................................................................ 6 5 Ordering Information ....................................................................................................... 7 6 Signal Table ...................................................................................................................... 7 7 Block Diagram .................................................................................................................. 8 8 Power-Up Initialization .................................................................................................... 9 9 Interface Description ..................................................................................................... 10 9.1 Address Space ....................................................................................................... 10 9.2 Page Length ........................................................................................................... 10 9.3 Drive Strength ....................................................................................................... 10 9.4 Power-on Status .................................................................................................... 10 10 Mode Register Definition ............................................................................................... 11 11 Command/Address Latching Truth Table ...................................................................... 12 11.1 Command Termination ......................................................................................... 13 12 Mode Register Operations ............................................................................................. 14 12.1 SPI MR Read Operation ......................................................................................... 14 12.2 SPI MR Write Operation ........................................................................................ 14 12.3 QPI MR Read Operation ........................................................................................ 15 12.4 QPI MR Write Operation ....................................................................................... 15 13 Read ID ........................................................................................................................... 16 13.1 SPI Read ID Operation ........................................................................................... 16 13.2 QPI Read ID Operation .......................................................................................... 17 14 Toggle Burst Length Operation ...................................................................................... 18 APM QSPI PSRAM Datasheet.pdf - Rev. 2.5 Nov 21, 2019 2 of 31 AP Memory reserves the right to change products and/or specifications without notice 2019 AP Memory. All rights reserved