Version 1.0 2009 PEX 8612 Features Features PE PEXX 8618612 V2 Viittaals ls oo 12-lane, 3-por12-lane, 3-port Pt PCCIe Gen2Ie Gen2 switch switch -- IntegratedIntegrated 5.0 5.0 GT/s SerDes GT/s SerDes 22 PCIe Gen2, 5.0GT/s 12-lane, 3- 3-porport Switch t Switch oo 19 x 19mm19 x 19mm , 32, 324-pin FCBGA packag4-pin FCBGA package e oo TyTyppiical Power: cal Power: 1.6 Watts 1.6 Watts TM The ExpressLane PEX 8612 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking PE PEXX 8618612 Key2 Key Fea Feattures ures interconnection to a wide variety of applications including oo StandarStandardds Compliant s Compliant workstations, storage systems, communications platforms, -- PCI Express BasPCI Express Basee Specification, r Specification, r2.0 2.0 (backwards(backwards comcomppatiblatiblee w/ w/ P PCCIe rIe r11.0a/1.0a/1..1)1) embedded systems, and intelligent I/O modules. The PEX 8612 is -- PCI Power Management Spec, rPCI Power Management Spec, r1.21.2 well suited for fan-out, aggregation, and peer-to-peer applications. -- Microsoft Vista Microsoft Vista Compliant Compliant -- Supports Access ControlSupports Access Control Servic Serviceess -- DDyynamic link-width connamic link-width conttrol rol High Performance & Low Packet Latency -- DDyynamnamiicc S SeerDesrDes s sppeed eed controcontroll The PEX 8612 architecture supports packet cut-thru with a maximum oo HighHigh P Perforerformamannce ce latency of 170ns (x4 to x4). This, combined with large packet memory and -- Non-blocking sNon-blocking swwitch fitch faabric bric non-blocking internal switch architecture, provides full line rate on all ports -- Full linFull line re raattee on on allall ports ports for performance-hungry applications such as servers and switch fabrics. -- Packet Cut-ThruPacket Cut-Thru w with 170ns maxith 170ns max pack packet et latlateencncy (x4y (x4 to to x4 x4) ) The low latency enables applications to achieve high throughput and -- 2KB Max Pay2KB Max Payllooaad Size d Size performance. In addition to low latency, the device supports a max payload -- Read PaRead Pacingcing (ba (bandwidth throndwidth throttlttlining) g) size of 2048 bytes, enabling the user to achieve even higher throughput. -- Dual-CasDual-Castt oo FlexiblFlexiblee Config Configuration uration -- Ports configurabPorts configurable le as x1, x2, x4as x1, x2, x4 Data Integrity -- Registers Registers configconfigurable withurable with strap strappping ing The PEX 8612 provides end-to-end CRC (ECRC) protection and Poison bit 22 pins, EEPROM, pins, EEPROM, II C, orC, or host software host software support to enable designs that require end-to-end data integrity. PLX also -- Lane andLane and polar polarityity reversreversal al supports data path parity and memory (RAM) error correction as packets -- ComComppatibleatible with with PCIe 1 PCIe 1..0a PM0a PM pass through the switch. oo Dual-Host & Fail-OverDual-Host & Fail-Over Suppor Supportt -- Configurable NoConfigurable Non-Transparenn-Transparent pt poort rt -- Moveable upstream port Moveable upstream port Flexible Register & Port Configuration -- Crosslink port Crosslink port capability capability The PEX 8612s 3 ports can be configured to lane widths of x1, x2, or x4. oo QuQualitality ofy of S Serviervice (ce (QoSQoS) ) Flexible buffer allocation, along with the device s flexible packet flow -- Eight traffEight traffiic clasc classes per porses per port t control, maximizes throughput for applications where more traffic flows in -- Weighted rouWeighted round-nd-robin source robin source port arbport arbitraitrationtion the downstream, rather than upstream, direction. Any port can be designated oo ReliabilitReliability, Avay, Availabilitilability, Sey, Servicrviceabiliteabilityy as the upstream port, which -- 2 Hot Plug Ports2 Hot Plug Ports with n with naativtive HP e HP Signals Signals x4x4 x4x4 22 can be changed dynamically. -- All ports hoAll ports hot pt plluugg cap capablablee thru thru I I C C The PEX 8612 also provides (Hot Plug Contr(Hot Plug Controollerller on on evereveryy poport) rt) -- ECRC andECRC and Poison bit support Poison bit support several ways to configure its -- Data PaData Path pth paaritrityy registers. The device can be PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612 PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612 -- MemoryMemory (RAM) Error (RAM) Error Correctio Correction n configured through -- INTA and FATAL ERR signals INTA and FATAL ERR signals 2 strapping pins, I C -- Advanced ErrorAdvanced Error Reporting Reporting -- PPoort Srt Sttatusatus b bitsits a and GPnd GPIO avaiIO availablabllee interface, host software, or x4x4 x4x4 x2x2 x2x2 -- Per port Per port errorerror diagnostics diagnostics an optional serial EEPROM. -- Performance MoPerformance Monitoringnitoring This allows for easy debug x4x4 Per port pPer port paayyllooaadd & h & headeader er counters counters during the development NTNT phase, performance monitoring during the PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612PEX 8612 operation phase, and driver or software upgrade. Figure 1 shows some of the x4x4 PEX 8612s common port Figure 1. Common Port Configurations configurations. Dual-Host & Failover Support Controller can be used to manage the hot-plug event of The PEX 8612 product supports a Non-Transparent its associated slot. Every port on the PEX 8612 is (NT) Port, which enables the implementation of multi- equipped with a hot-plug control/status register to host systems and intelligent I/O modules in storage, support hot-plug capability through external logic via the 2 communications, and blade server applications. The NT I C interface. port allows systems to isolate host memory domains by presenting the SerDes Power and Signal Management PPPPPriPriPriPrirrrriiiimmmmmmmmaryaryaryaryary Hoary Hoary Hoary Ho H H H Hoooostststststststst SSSSSSSSeeeeeeeeccccccccondaondaondaondaondaondaondaondaryryryryryryryry H H H H H H H Hoooooooosssssssstttttttt processor subsystem The PEX 8612 supports software control of the SerDes CPCPCPCPUUUU CPCPCPCPUUUU CPCPCPCPUUUU CPCPCPCPUUUU as an endpoint rather outputs to allow optimization of power and signal than another memory strength in a system. The PLX SerDes implementation system. Base address supports four levels of power off, low, typical, and Root Root Root Root Root Root Root Root registers are used to high. The SerDes block also supports loop-back modes CoCoCoCoCoCoCoComplmplmplmplmplmplmplmpleeeeeeeexxxxxxxx translate addresses and advanced reporting of error conditions, which doorbell registers are enables efficient management of the entire system. NTNTNT used to send interrupts between PPPEX 8612EX 8612EX 8612 Interoperability PEPEPEX 8612X 8612X 8612 NNNon-Tranon-Tranon-Transparentsparentsparent the address domains The PEX 8612 is designed to be fully compliant with the PorPorPorttt and scratchpad registers PCI Express Base Specification r2.0, and is backwards EEEEEEEEnd nd nd nd nd nd nd nd (accessible by both compatible to PCI Express Base Specification r1.1 and PoPoPoPointintintint PoPoPoPointintintint CPUs) allow inter- r1.0a. Additionally, it supports auto-negotiation, lane FigureFigure 2.2. Non Non--TTrransparenansparent Port Portt processor reversal, and polarity reversal. Furthermore, the communication (see Figure 2). In a two-port PEX 8612 is designed for Microsoft Vista compliance. configuration (as in Figure 1), the PEX 8612 can serve All PLX switches undergo thorough interoperability as an NT buffer, isolating two host domains via two x4 testing in PLXs Interoperability Lab and compliance links. testing at the PCI-SIG plug-fest. Dual Cast The PEX 8612 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one Applications ingress port to two egress ports allowing for higher Suitable for host-centric as well as peer-to-peer traffic performance in dual-graphics, storage, security, and patterns, the PEX 8612 can be configured for a broad redundant applications. range of form factors and applications. Read Pacing Host Centric Fan-out The Read Pacing feature allows users to throttle the The PEX 8612, with its symmetric or asymmetric lane amount of read requests being made by downstream configuration capability, allows user-specific tuning to a devices. When a downstream device requests several variety of host-centric applications. Figure 3 shows a long reads back-to-back, the Root Complex gets tied up typical workstation design where the root complex in serving this downstream port. If this port has a narrow provides a PCI Express link that needs to be expanded to link and is therefore slow in receiving these read packets a larger number of smaller ports for a variety of I/O from the Root Complex, then other downstream ports functions. In this example, the PEX 8612 has a 4-lane may become starved thus, impacting performance. The upstream port and two downstream ports using x4 links. Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. The PEX 8612 can also be used to create PCIe Gen1 (2.5 Gbps) ports. The PEX 8612 is backwards compatible Hot Plug for High Availability with PCIe Gen1 devices. Therefore, the PEX 8612 Hot plug capability allows users to replace hardware enables a Gen 2 native Chip Set to fan-out to Gen 1 modules and perform maintenance without powering endpoints. In Figure 3, the PCIe slots connected to the down the system. The PEX 8612 hot plug capability PEX 8612s downstream ports can be populated with feature makes it suitable for High Availability (HA) either PCIe Gen1 or PCIe Gen 2 devices. Conversely, applications. Two downstream ports include a Standard the PEX 8612 can also be used to create Gen 2 ports on Hot Plug Controller. If the PEX 8612 is used in an a Gen 1 native Chip Set in the same fashion. application where one or more of its downstream ports connect to PCI Express slots, each ports Hot Plug