DATA SHEET SILICON POWER MOS FET NE552R479A 3.0 V OPERATION SILICON RF POWER LDMOS FET FOR 2.45 GHz 0.4 W TRANSMISSION AMPLIFIERS DESCRIPTION The NE552R479A is an N-channel silicon power laterally diffused MOS FET specially designed as the transmission power amplifier for 3.0 V WLL products. Dies are manufactured using our NEWMOS2 technology (our WSi gate laterally diffused MOS FET) and housed in a surface mount package. This device can deliver 26.0 dBm output power with 45% power added efficiency at 2.45 GHz under the 3.0 V supply voltage. FEATURES High output power : Pout = 26.0 dBm TYP. (VDS = 3.0 V, IDset = 200 mA, f = 2.45 GHz, Pin = 19 dBm) High power added efficiency : add = 45% TYP. (VDS = 3.0 V, IDset = 200 mA, f = 2.45 GHz, Pin = 19 dBm) High linear gain : GL = 11 dB TYP. (VDS = 3.0 V, IDset = 200 mA, f = 2.45 GHz, Pin = 10 dBm) Surface mount package : 5.7 5.7 1.1 mm MAX. Single supply : VDS = 2.8 to 6.0 V APPLICATIONS Digital cellular phones : 3.0 V GSM1900 Pre Driver Analog cellular phones : 2.8 V AMPS Handsets TM Bluetooth applications : 3.0 V Class 1 Devices Others : 3.0 V Two-Way Pagers ORDERING INFORMATION Part Number Package Marking Supplying Form NE552R479A-T1 79A AW 12 mm wide embossed taping Gate pin face the perforation side of the tape Qty 1 kpcs/reel NE552R479A-T1A 12 mm wide embossed taping Gate pin face the perforation side of the tape Qty 5 kpcs/reel Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: NE552R479A-A Caution: Observe precautions when handling because these devices are sensitive to electrostatic discharge Document No. PU10124EJ03V0DS (3rd edition) The mark shows major revised points. Date Published July 2003 CP(K) NE552R479A ABSOLUTE MAXIMUM RATINGS (TA = +25C) Parameter Symbol Ratings Unit Drain to Source Voltage VDS 15.0 V Gate to Source Voltage VGS 5.0 V Drain Current ID 300 mA Note Drain Current (Pulse Test) ID 600 mA Total Power Dissipation Ptot 10 W Channel Temperature Tch 125 C Storage Temperature Tstg 55 to +125 C Note Duty Cycle 50%, Ton 1 s RECOMMENDED OPERATING CONDITIONS Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Drain to Source Voltage VDS 2.8 3.0 6.0 V Gate to Source Voltage VGS 0 2.0 3.0 V Drain Current ID Duty Cycle 50%, Ton 1 s 200 500 mA Input Power Pin f = 2.45 GHz, VDS = 3.0 V 18 19 25 dBm ELECTRICAL CHARACTERISTICS (TA = +25C, unless otherwise specified, using NEC standard test fixture) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Gate to Source Leak Current IGSS VGS = 5.0 V 100 nA Drain to Source Leakage Current IDSS VDS = 6.0 V 100 nA (Zero Gate Voltage Drain Current) Gate Threshold Voltage Vth VDS = 3.5 V, ID = 1 mA 1.0 1.4 1.9 V Thermal Resistance Rth Channel to Case 10 C/W Transconductance Gm VDS = 3.5 V, ID = 100 mA 0.4 S Drain to Source Breakdown Voltage BVDSS IDSS = 10 A 15 18 V Output Power Pout f = 2.45 GHz, VDS = 3.0 V, 24.0 26.0 dBm mA Drain Current ID Pin = 19 dBm, 230 Power Added Efficiency add IDset = 200 mA (RF OFF), Note1 35 45 % Note2 dB Linear Gain GL 11 Notes 1. DC performance is 100% testing. RF performance is testing several samples per wafer. Wafer rejection criteria for standard devices is 1 reject for several samples. 2. Pin = 10 dBm 2 Data Sheet PU10124EJ03V0DS